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检索条件"任意字段=Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays"

共 162 条记录，以下是71-80 订阅

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Application specific instruction sets and their impact on the design space requirements of a hardware Java Virtual Machine

Application specific instruction sets and their impact on th...

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19th IEEE/IFIP international symposium on Rapid System Prototyping

作者： Wood, Ryan Libby, Joseph C. Kent, Kenneth B. Univ New Brunswick Fac Comp Sci Fredericton NB E3B 5A3 Canada

ISBN: (纸本)9780769531809

the widespread availability of field programmable gate arrays (FPGA) coupled with different implementations of "soft-core" processors has created a need to find new methods for optimizing these processors. Because design space is limited on most FPGA's and the maximum clock rate of these processors is heavily bound to the overall size and resource usage it is necessary to find ways to minimize the size of the processor. One such way to minimize the size of a "soft-core" processor is to customize the instruction set on Which it operates. Removing instructions that are supported but not utilized by target applications may provide a reduction in design space usage as well as an increase in maximum clock frequencies for the processor.

关键词： field programmable gate arrays (FPGA)

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Novel predictable segmented FPGA routing architecture

Novel predictable segmented FPGA routing architecture

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Ochotta, Emil S. Crotty, Patrick J. Erickson, Charles R. Huang, Chih-Tsung Jayaraman, Rajeev Li, Richard C. Linoff, Joseph D. Ngo, Luan Nguyen, Hy V. Pierce, Kerry M. Wieland, Douglas P. Zhuang, Jennifer Nance, Scott S. Xilinx Inc San Jose United States

In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented, novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.

关键词： field programmable gate arrays

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High-performance, energy-efficient platforms in-socket FPGA accelerators

High-performance, energy-efficient platforms in-socket FPGA ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Liu Oliver, Neal Bhushan, Chitlur Qigang, Wang Chen, Alvin Wenbo, Shen Zhihong, Yu Sheiman, Arthur McCallum, Ian Grecco, Joseph Mitchel, Henry Dong, Liu Gupta, Prabhat Intel Corporation

ISBN: (纸本)9781605584102

Growing demand for energy-efficient, high-performance systems has resulted in the growth of innovative heterogeneous computing system architectures that use FPGAs. FPGA-based architectures enable designers to implement custom instruction streams executing on potentially thousands of compute elements. Traditionally, FPGAs have been used as compute elements on PCI devices;however, this does not allow the FPGAs to be coprocessors. this paper describes a high-performance system architecture that is based on the Intel Xeon platform in which one or more FPGAs, acting as application accelerators, replace one or more processors in a dual/multi-processor (DP/MP) platform. the FPGA is thus connected directly to the Front Side Bus (FSB) and enjoys the same privileges as a processor, i.e., full participation in the coherency protocol, unrestricted access to system memory and to other processors via the high bandwidth, and low latency connection to the FSB. In addition, we also describe a software layer called the "Accelerator Abstraction Layer (AAL)", which provides a uniform, hardware- and/or platform-independent application interface. Applications written on AAL can be ported to multiple platforms that have different types of accelerators and the application does not have to be modified. In addition, the AAL also enables the developer/user to reprogram the FPGA on the fly (analogous to an operating system context switch) thereby utilizing the programmable nature of the FPGA. the resulting hardware/software stack creates a flexible and powerful platform for accelerator innovation and deployment. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Analysis of the effect of LUT size on FPGA area and delay us...

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6th international symposium on Quality Electronic Design

作者： Gao, HX Yang, YT Ma, XH Dong, G Xidian Univ Microelect Inst Xian 710071 Peoples R China

ISBN: (纸本)0769523013

Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. the effect of LUT size on FPGA area and performance is studied. Results show optimal L UT size conclusion from computation models is same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.

关键词： field programmable gate arrays (FPGA)

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FPGA architecture for static background subtraction in real time

FPGA architecture for static background subtraction in real ...

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SBCCI 2006 - 19th symposium on Integrated Circuits and Systems Design

作者： Oliveira, Jozias Printes, André Freire, R.C.S. Melcher, Elmar Silva, Ivan S. S. Genius Institute of Technology Distrito Industrial Av. Açal 875 69075-904 Manaus AM Brazil Federal University of Campina Grande Rua Aprígio Veloso 882 58109-970 Campina Grande PB Brazil Federal University of Para Rua Augusto Corrêa 01 66075-110 Belém PA Brazil

ISBN: (纸本)1595934790

Background subtraction is a method typically used to segment moving regions in image sequences taken from a static camera by comparing each new frame to a model of the scene background. In this paper, we present an FPGA architecture for background subtraction, taking advantage of the data and logical parallel opportunities offered by a field programmable gate array (FPGA) architecture. At a clock rate of 40 MHz, the architecture can process 30 frames per second, where the image resolution is 240 × 120. the capability of the system is demonstrated for several tests and video sequences. Copyright 2006 acm.

关键词： field programmable gate arrays

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the P4→NetFPGA Workflow for Line-Rate Packet Processing 19

The P4→NetFPGA Workflow for Line-Rate Packet Processing

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Ibanez, Stephen Brebner, Gordon McKeown, Nick Zilberman, Noa Stanford Univ Stanford CA 94305 USA Xilinx Labs San Jose CA USA Univ Cambridge Cambridge England

ISBN: (纸本)9781450361378

P4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. the goal of the work presented here is to make it easier for engineers, researchers and students to learn how to program using P4, and to build prototypes running on real hardware. Our target is the NetFPGA SUME platform, a 4 x 10 Gb/s PCIe card designed for use in universities for teaching and research. Until now, NetFPGA users have needed to learn an HDL such as Verilog or VHDL, making it off limits to many software developers and students. therefore, we developed the P4 -> NetFPGA workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the NetFPGA SUME board. the P4 -> NetFPGA workflow is built upon the Xilinx P4-SDNet compiler and the NetFPGA SUME open source code base. In this paper, we provide an overview of the P4 programming language and describe the P4 -> NetFPGA workflow. We also describe how the workflow is being used by the P4 community to build research prototypes, and to teach how network systems are built by providing students with hands-on experience working with real hardware.

关键词： programmable data-planes fpga p4

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VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

VPR 5.0: FPGA CAD and architecture exploration tools with si...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Luu, Jason Kuon, Ian Jamieson, Peter Campbell, Ted Ye, Andy Fang, Wei Mark Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

the VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. this paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing architectures [29, 4, 16]. Single-driver routing has significantly different architectural and electrical properties from the multi-driver approach previously modelled, and is now employed in the majority of FPGAs sold. Second, the new release can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in FPGAs. third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. the method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation 13

Artificial neural network implementation on a single FPGA of...

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13th international symposium on System Synthesis (ISSS 2000)

作者： Gadea, R Cerdá, J Ballester, F Mocholí, A Univ Politecn Valencia Dept Elect Engn Valencia 46022 Spain

ISBN: (纸本)0769507662

the paper describes the implementation of a systolic array for a multilayer perceptron on a Virtex XCV400 FPGA with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. Parallelism is better exploited because both forward and backward phases can be performed simultaneously. We can implement very large interconnection layers by using large Xilinx devices with embedded memories alongside the projection used in the systolic architecture. these physical and architectural features - together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL - create an easy, flexible, and fast method of designing a complete ANN on a single FPGA. the result offers a high degree of parallelism and fast performance.

关键词： Arithmetic Artificial neural networks Backpropagation algorithms field programmable gate arrays Logic arrays Logic devices Neural networks Neurons Signal processing algorithms Systolic arrays

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Design of a Single Event Upset (SEU) mitigation technique for programmable devices 06

Design of a Single Event Upset (SEU) mitigation technique fo...

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7th international symposium on Quality Electronic Design

作者： Baloch, S. Arslan, T. Stoica, A. Alba Centre Inst Syst Level Integrat Alba Campus Livingston EH54 7EG Scotland Univ Edinburgh Sch Elect & Engg Edinburgh EH8 9YL Midlothian Scotland NASA Jet Propuls Lab Pasadena CA 91109 USA

ISBN: (纸本)0769525237

this paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. the design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. the proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. this approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. the result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.

关键词： Single event upset field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation programmable logic arrays Latches

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