In this paper, we present a model of an UHF RFID tag for system and application level simulation. The prime focus is on the radio frequency link. The model describes carrier frequency dependent behavior based on the e...
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ISBN:
(纸本)078039352X
In this paper, we present a model of an UHF RFID tag for system and application level simulation. The prime focus is on the radio frequency link. The model describes carrier frequency dependent behavior based on the envelope signal description with the value of the carrier frequency being time invariant parameter. The background idea is to model the ASIC load current as a time variant function of the load voltage and to keep ASIC parallel reactance time invariant.
The focus of this research is on the testability analysis of the operators in the behavioral description prior to synthesis. The controllabilities of the inputs to an operator and the observabilities of the outputs of...
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ISBN:
(纸本)0769507867
The focus of this research is on the testability analysis of the operators in the behavioral description prior to synthesis. The controllabilities of the inputs to an operator and the observabilities of the outputs of the operation are computed from the value ranges of the variables that serve as the inputs and outputs. The proposed technique uses a formal dataflow, analysis instead of profiling or simulation, to accurately pin-point the hard-to-test operations in the design. Variable selection for testability enhancement of hard-to-test operations is accomplished based on the computed testability measures for all the involved operations in the behavioral description. The insertion of appropriate testability enhancements is then performed for the hard-to-test operators to achieve significantly higher test coverages, while keeping the design area-performance overhead to a minimum.
The proceedings contains 16 papers from the proceedings of the 3rd acminternationalworkshop on modeling, Analysis and simulation of Wireless and Mobile Systems. The topics discussed include: analytical comparison of...
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ISBN:
(纸本)1581133049
The proceedings contains 16 papers from the proceedings of the 3rd acminternationalworkshop on modeling, Analysis and simulation of Wireless and Mobile Systems. The topics discussed include: analytical comparison of different GPRS introduction strategies;WAP traffic;effects of circuit switched transmissions over GPRS performance;estimation of reverse-link capacity for multiband DS-CDMA systems and multicast tree construction and flooding in wireless ad hoc networks.
In this paper, we describe a novel top/down methodology for behavioral and structural modeling of multi domain microsystems. The study case is an integrated power harvesting circuit used for supplying power to nodes i...
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ISBN:
(纸本)9781424415670
In this paper, we describe a novel top/down methodology for behavioral and structural modeling of multi domain microsystems. The study case is an integrated power harvesting circuit used for supplying power to nodes in wireless sensor networks. The system includes an analog circuit, a piezoelectric MEMS generator and a storage capacitor. The classical validation of such systems by separate simulation of each element: FEM analysis for mechanical part and traditional circuit-simulators for electrical part does not offer the possibility to predict the behavior of the complete system. To overcome such limitations, we propose to use a simulation environment based on VHDL-AMS and SPICE languages.
In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavior...
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ISBN:
(纸本)078039352X
In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.
In this paper, a fast and accurate technique for modeling and simulation of clock jitter in Continuous-Time sigma-delta (ΣΔ) modulators is introduced. In addition to its high speed compared to the traditional jitter...
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We propose a simulation-based approach for performance modeling of parallel applications on high-performance computing platforms. Our approach enables full-system performance modeling: (1) the hardware platform is rep...
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ISBN:
(纸本)9780738110707
We propose a simulation-based approach for performance modeling of parallel applications on high-performance computing platforms. Our approach enables full-system performance modeling: (1) the hardware platform is represented by an abstract yet high-fidelity model;(2) the computation and communication components are simulated at a functional level, where the simulator allows the use of the components native interface;this results in a (3) fast and accurate simulation of full HPC applications with minimal modifications to the application source code. This hardware/software hybrid modeling methodology allows for low overhead, fast, and accurate exascale simulation and can be easily carried out on a standard client platform (desktop or laptop). We demonstrate the capability and scalability of our approach with High Performance LINPACK (HPL), the benchmark used to rank supercomputers in the TOP500 list. Our results show that our modeling approach can accurately and efficiently predict the performance of HPL at the scale of the TOP500 list supercomputers. For instance, the simulation of HPL on Frontera takes less than five hours with an error rate of four percent.
To enable full chip functional verification, critical system building blocks need to be abstracted and simplified using behavioral models. Charge pump voltage converters are highly active circuits and act as bottle ne...
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ISBN:
(纸本)9781424415670
To enable full chip functional verification, critical system building blocks need to be abstracted and simplified using behavioral models. Charge pump voltage converters are highly active circuits and act as bottle necks when integrated in SoC verification simulations. In this paper, a charge pump circuit designed by STMicroelectronics will be modeled using VHDL-AMS. Using this model, the whole SoC can be simulated by ADVance MS (TM).
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