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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Efficient VHDL implementation of an upscaling function for real time video applications

Efficient VHDL implementation of an upscaling function for r...

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2019 IEEE international symposium on Circuits and Systems, ISCAS 2019

作者： Rubio-Ibáñez, Pablo Martínez-Álvarez, José Javier Doménech-Asensi, Ginés Dpto. de Electronica Tecnología de Computadoras y Proyectos Universidad Politécnica de Cartagena Cartagena Spain

ISBN: (纸本)9781728103976

This paper describes the design and the implementation of a high-performance area-efficient upscaling function on a FPGA. The proposed function performs the resizing of real time video images, from M x N pixels to 2M x 2N pixels, using a bilinear interpolation method. The hardware implementation has been carried out using an RTL structural description in VHDL, to maximize the use of the specific resources of the FPGA, especially its memory resources (BRAM). For this purpose, an optimized memory access schema, that allows the best performance of the architecture with the least use of hardware resources, is proposed. Details of the design and the implementation on a Zynq UltraScale+ MPSoC are given, as well as speed-performance and area utilization. The proposed solution significantly improves the results achieved using this schema compared with those obtained using the Resize function from the Xilinx OpenCV library, when both are configured to obtain the same spatial transformation. © 2019 IEEE

关键词： field programmable gate arrays (FPGA)

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Message-Oriented Devices on FPGAs 29

Message-Oriented Devices on FPGAs

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Baumela, Thomas Gruber, Olivier Muller, Olivier Pétrot, Frédéric Univ. Grenoble Alpes CNRS Grenoble Institute of Engineering TIMA Grenoble38000 France

ISBN: (纸本)9781538675571

Embedded systems increasingly include an FPGA for performance or power efficiency. Fortunately, FPGA makers provide efficient tools to develop and assemble multiple Intellectual Properties (IPs) as devices on FPGAs. Unfortunately, the integration challenge does not stop there, hardware devices are only usable if they have available software device drivers executing on the processor subsystem. To better approach this end-to-end integration challenge, across both hardware and software, we argue that both sides need to evolve. We propose to take a step towards message-based interfaces for hardware devices integrated on an FPGA. Our goal is to deliver to the FPGA market the plug-and-play value of the USB stack with essentially no performance overhead, negligible power increase, and a reasonable surface cost. We have implemented our proposal on the Xilinx Zynq SoC, combining ARM cores and an FPGA, demonstrating the feasibility of the approach. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Network-on-Chip programmable Platform in VersalTM ACAP Architecture 19

Network-on-Chip Programmable Platform in VersalTM ACAP Archi...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Ian Swarbrick Dinesh Gaitonde Sagheer Ahmad Brian Gaide Ygal Arbel Xilinx Inc. San Jose CA USA Xilinx Inc. Longmont CO USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： versal stacked silicon ssit fpga acap

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TOF estimation based on compressed real-time histogram builder for SPAD image sensors

TOF estimation based on compressed real-time histogram build...

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2019 IEEE international symposium on Circuits and Systems, ISCAS 2019

作者： Vornicu, I. Darie, A. Carmona-Galán, R. Rodríguez-Vázquez, Á. Instituto de Microelectrónica de Sevilla IMSE CNM [CSIC Universidad de Sevilla Spain

ISBN: (纸本)9781728103976

This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range. © 2019 IEEE

关键词： field programmable gate arrays (FPGA)

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On Feasibility of FPGAs Without Dedicated programmable Interconnect Structure 19

On Feasibility of FPGAs Without Dedicated Programmable Inter...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Anastasiia Kucherenko Stefan Nikolic Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781450361378

It is a well known fact that a great majority of FPGA chip area goes into the programmable interconnect structure. Since area consumption is mostly proportional to the level of flexibility the interconnect structure offers, how much of this flexibility is really needed for the implementation of any design of interest is a logical question to pose. Going one step further, one may wonder if a dedicated programmable interconnect structure is even necessary. This work answers exactly this second question by providing constructive capability proofs, for a broad class of FPGA architectures composed solely of look-up tables (LUTs) connected in a fixed manner, to implement any circuit graph. Our proposed architectures consist of identical cells of LUTs with fixed connections, arranged on a 2D grid. Direct wires between cell input and output pins are also allowed, enabling long uninterrupted connections. We begin by formalizing the above architecture class, and then describe an algorithm capable of mapping any circuit on one specific member of it, in which each cell consists of a single 4-LUT. We derive area and runtime bounds for the algorithm, and finally extend it to be applicable to any architecture in which no LUT receives more than K - 4 inputs from within the cell (K is LUT size) and the number of sink LUTs of the cell does not exceed the number of source LUTs. Presented algorithms serve to answer the posed question, but, due to area-inefficiency, do not have much practical value at this point.

关键词： periodic graphs routing algorithms universality proofs fixed interconnect hard-wired fpgas

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Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS 19

Efficient FPGA Implementation of Conjugate Gradient Methods ...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sahithi Rampalli Natasha Sehgal Ishita Bindlish Tanya Tyagi Pawan Kumar International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450361378

In conjugate gradient method to solve partial differential equations, matrix vector operations are required in each iteration; these matrix vector operations can be implemented as 5 point finite difference stencil operations on the grid without explicitely constructing the matrix. We show that a pipelined and superscalar design using high level synthesis (HLS) leads to a significant reduction in latencies for two variants of conjugate gradient methods considered. When comparing these two, we show that the second method has roughly two times lower latency than the former given the same degree of superscalarity. These reductions in latencies for the newer variant of CG is due to parallel implementations of stencil operation on subdomains of the grid, and due to overlap of these stencil operations with dot product operations. In a superscalar design for the stencil operation, the computational domain needs to be partitioned, and boundary data needs to be copied, which requires padding. We propose a novel traversal of the grid for 2D domain decomposition that leads to reduction in latency cost involved with padding. The FPGA implementation of CG is roughly 7 times faster than state-of- the-art sequential implementation, and roughly 4 times faster than state-of-the-art CUDA library parallel implementation for the linear system of dimension 10000 x 10000.

关键词： fpga high level synthesis laplace system pipelining superscalarity conjugate gradient

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Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper 29

Rapid Prototyping of Parameterized Rotated and Cyclic Q Dela...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Waqas, Muhammad Jafri, Atif Raza Baghdadi, Amer Najam-Ul-Islam, M. Bahria University Islamabad Pakistan Lab-STICC laboratory IMT Atlantique Brest France

ISBN: (纸本)9781538675571

Rotated and Cyclic Q Delayed (RCQD) modulation is one of the signal processing schemes which, once used on the transmitter side, provides performance improvement on receiver side in case of fading channel conditions with erasures. However, an efficient hardware solution in terms of low area and high throughput is mandatory to get benefit from this modulation technique. In this paper we have implemented a parameterized hardware architecture of most recent RCQD demapping technique supporting different constellations. In addition to the description of the proposed hardware architecture, rapid prototyping flow based on LabVIEW FPGA is described which is useful to explore different design schemes in short period of time. The implementation results are achieved by FPGA prototyping while targeting NI-USRP RIO hardware equipment. By comparing our rapidly prototyped parameterized RCQD demapper with other state-of-the-art implementation schemes, it is shown that our prototyped demapper consumed lesser hardware resources and achieved higher throughput with very short design time. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing 29

PyXEL: An Integrated Environment for the Analysis of Fault E...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Bozzoli, Ludovica De Sio, Corrado Sterpone, Luca Bernardeschi, Cinzia Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy Department of Information Engineering University of Pisa Pisa Italy

ISBN: (纸本)9781538675571

In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. Thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. The increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. The analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC 29

Vicilogic 2.0: Online Learning and Prototyping of Digital Sy...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Morgan, Fearghal O'loughlin, Declan Audiger, Jeremy Boyer, Yohan Timlin-Canning, Niall Kepa, Krzysztof Cawley, Seamus Gallivan, Ian Bako, László Callaly, Frank National University of Ireland Galway Ireland Sapientia Hungarian University of Transylvania Romania

ISBN: (纸本)9781538675571

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE). © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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OLAF′17: Third international Workshop on Overlay Architectures for FPGAs 17

OLAF′17: Third International Workshop on Overlay Architectu...

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acm/sigda international symposium on field-programmable gate arrays

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450343541

The Third international Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with FPGA 2017: The 25th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunites provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers with panel discussions with prominent experts in the field.

关键词： FPGA Overlay architecture

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