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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Reconfigurable Thermoelectric Generators for Vehicle Radiators Energy Harvesting 22

Reconfigurable Thermoelectric Generators for Vehicle Radiato...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Baek, Donkyu Ding, Caiwen Lin, Sheng Shin, Donghwa Kim, Jaemin Lin, Xue Wang, Yanzhi Chang, Naehyuck Korea Adv Inst Sci & Technol Daejeon South Korea Syracuse Univ Syracuse NY USA Yeungnam Univ Gyongsan South Korea Seoul Natl Univ Seoul South Korea Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781509060238

Conventional internal combustion engine vehicles (ICEV) generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The heat energy maintains the engine temperature for efficient combustion as a good aspect, but the amount of heat generation is excessive and eventually breaks the engine components unless advanced cooling system technologies are supported such as high- capacity radiators, elaborated water jackets, high- flow rate coolant pumps, etc. The excessive heat dissipation plays a key role on a poor fuel economy, but reclamation of the heat energy has not been a main focus of vehicle design. This work is first to propose a cross-layer, system-level solution to enhance thermoelectric generator (TEG) array efficiency introducing online reconfiguration of TEG modules. The proposed method is useful to any sort of TEG array to reclaim wasted heat energy because cooling and exhaust systems generally have different inlet and outlet temperatures. In this paper, we deploy the proposed method to vehicle radiator heat energy harvesting, which does not affect the vehicle performance while exhaust heat energy harvesting may disturb the combustion and emission control integrity. We introduce a novel TEG reconfiguration and maximize the TEG array output in spite of dynamic change of the coolant flow rate and temperature, which results in a huge variation in the coolant temperature distribution of inside the radiator. The proposed method enables all the TEG modules to run at or close to their maximum power points (MPP) under dynamically changing vehicle operating conditions. Experimental results show up to a 34% enhancement compared with a fixed array structure, which is a common practice.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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SceneMan: Bridging Mobile Apps with System Energy Manager via Scenario Notification 22

SceneMan: Bridging Mobile Apps with System Energy Manager vi...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Li, Li Wang, Jun Wang, Xiaorui Ye, Handong Hu, Ziang Ohio State Univ Columbus OH 43210 USA Huawei US R&D Santa Clara CA USA

ISBN: (纸本)9781509060238

Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads 22

Online Tuning of Dynamic Power Management for Efficient Exec...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Bantock, James R. B. Tenentes, Vasileios Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Dept Elect & Comp Sci Southampton Hants England

ISBN: (纸本)9781509060238

Modern mobile devices contain powerful MultiProcessor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Generalized column distances for convolutional codes

Generalized column distances for convolutional codes

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IEEE international symposium on Information Theory (ISIT)

作者： Cardell, Sara D. Firer, Marcelo Napp, Diego Univ Estadual Campinas Inst Matemat Estat & Comp Cient Campinas SP Brazil Univ Aveiro Dept Matemat Aveiro Portugal

ISBN: (纸本)9781509040964

In this work, we adapt the notion of generalized Hamming weight of block codes to introduce the novel concept of generalized column distances for convolutional codes. This can be considered as an extension of the work done in [18] on the generalized Hamming weights for free distance of convolutional codes. We also introduce the concept of Almost-MDP and Near-MDP convolutional code. The problem of constructing convolutional codes with design generalized column distances remains an interesting open problem that requires further research.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Power Optimizations in MTJ-based Neural Networks through Stochastic Computing 22

Power Optimizations in MTJ-based Neural Networks through Sto...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mondal, Ankit Srivastava, Ankur Univ Maryland Dept Elect & Comp Engn College Pk MD 20783 USA

ISBN: (纸本)9781509060238

Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. Spintronic devices, such as Magnetic Tunnel Junctions (MTJs), are capable of replacing CMOS in memory and logic circuits. In this work, we propose an energy-efficient use of MTJs, which exhibit probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, error resilient target applications of NNs allow us to introduce Approximate Computing, a framework wherein accuracy of computations is traded-off for substantial reductions in power consumption. We propose approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of our MTJ-SNG, to achieve energy-efficiency. We design an algorithm that can perform such approximations within a given error tolerance in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. To give a perspective of the effectiveness of our approach, a 43% reduction in power consumption was obtained with less than 1% accuracy loss on a standard classification problem, with 26% being brought about by the proposed algorithm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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OLAF′16: Second international Workshop on Overlay Architectures for FPGAs 16

OLAF′16: Second International Workshop on Overlay Architect...

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450338561

The Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: The 24th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.

关键词： FPGA Overlay architecture

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Parking of Nonholonomic Mobile Robots via Switched Control in the Discrete Time Domain 26

Parking of Nonholonomic Mobile Robots via Switched Control i...

引用

26th IEEE international symposium on Industrial Electronics (ISIE)

作者： Li, Zhengguo Zou, Ying Wen, Changyun Inst Infocomm Res Robot Dept Singapore 138632 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)9781509014125

Due to nonholonomic constraints, it is challenging to study parking of mobile robots, especially in the discrete time domain. In this paper, a switched controller is designed in the discrete time domain for the parking of mobile robots towards a target pose. The proposed controller is implemented by using the concept of a sequence of discrete time instances. The angular velocity of the robot is fixed between two discrete time instances to guarantee the controllability of the error dynamics. Moreover, the conventional pole assignment is employed to asymptotically stabilize the system. Meanwhile, instead of moving towards the target pose, the mobile robot is driven to approach the intermediated poses, which are constructed using positions of the robot at a predefined set of discrete time instances and the target pose. The introduction of the time-varying intermediated poses reduces the risk of high gain. Simulation results demonstrate the effectiveness of the proposed switched controller for parking of mobile robots.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Multi-Cell Aware Opportunistic Random Access

Multi-Cell Aware Opportunistic Random Access

引用

IEEE international symposium on Information Theory (ISIT)

作者： Lin, Huifa Shin, Won-Yong Dankook Univ Commun & Networking Lab Yongin 16890 South Korea Dankook Univ Comp Sci & Engn Yongin 16890 South Korea

ISBN: (纸本)9781509040964

We propose a decentralized multi -cell aware opportunistic random access (MA-ORA) protocol that almost achieves the optimal throughput scaling in a K-cell random access network with one access point (AP) and N users in each cell. Under our MA-ORA protocol, users opportunistically transmit with a predefined physical layer data rate in a decentralized manner if the desired signal power to the serving AP is sufficiently large and the generating interference power to other APs is sufficiently small. It is proved that the aggregate throughput scales as K/e (1 - is an element of) log(SNR log N) in a high signal-to-noise ratio (SNR) regime if N scales faster than SNR1-delta (K-1) for small constants is an element of, delta > 0. Our analytical result is validated by computer simulations.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Two-Way Interference Channel Capacity: How to Have the Cake and Eat it Too

Two-Way Interference Channel Capacity: How to Have the Cake ...

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IEEE international symposium on Information Theory (ISIT)

作者： Suh, Changho Cho, Jaewoong Tse, David Korea Adv Inst Sci & Technol EE Daejeon South Korea Stanford Univ EE Stanford CA 94305 USA

ISBN: (纸本)9781509040964

Two-way communication is prevalent and its fundamental limits are first studied in the point-to-point setting by Shannon [1]. One natural extension is a two-way interference channel (IC) with four independent messages: two associated with each direction of communication. In this work, we explore a deterministic two-way IC which captures key properties of the wireless Gaussian channel. Our main contribution lies in the complete capacity region characterization of the two-way IC (w.r.t. the forward and backward sum-rate pair) via a new achievable scheme. One surprising consequence of this result is that not only we can get an interaction gain over the one-way non-feedback capacities, we can sometimes get all the way to perfect feedback capacities in both directions simultaneously.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Towards PVT-Tolerant Glitch-Free Operation in FPGAs 16

Towards PVT-Tolerant Glitch-Free Operation in FPGAs

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Huda, Safeen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450338561

Glitches are unnecessary transitions on logic signals that needlessly consume dynamic power. Glitches arise from imbalances in the combinational path delays to a signal, which may cause the signal to toggle multiple times in a given clock cycle before settling to its final value. In this paper, we propose a low-cost circuit structure that is able to eliminate a majority of glitches. The structure, which is incorporated into the output buffers of FPGA logic elements, suppresses pulses on buffer outputs whose duration is shorter than a configurable time window (set at the time of FPGA configuration). Glitches are thereby eliminated "at the source" ensuring they do not propagate into the high-capacitance FPGA interconnect, saving power. An experimental study, using Altera commercial tools for power analysis, demonstrates that the proposed technique reduces 70% of glitches, at a cost of 1% reduction in speed performance.

关键词： field programmable gate arrays (FPGA)

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