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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是171-180 订阅

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Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper 16

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGA...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Schmit, Herman Huang, Randy Intel Corporation San JoseCA United States

ISBN: (纸本)9781450341851

Intel's Xeon roadmap includes package-integrated FPGAs in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that FPGAs are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the FPGA. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications. © 2016 Authors.

关键词： field programmable gate arrays (FPGA)

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FPGA 2013 - proceedings of the 2013 acm/sigda international symposium on field programmable gate arrays

FPGA 2013 - Proceedings of the 2013 ACM/SIGDA International ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

ISBN: (纸本)9781450318877

The proceedings contain 29 papers. The topics discussed include: accelerating subsequence similarity search based on dynamic time warping distance with FPGA;video-rate stereo matching using Markov random field TRW-S inference on a hybrid CPU+FPGA computing platform;fully-functional FPGA prototype with fine-grain programmable body biasing;sensing nanosecond-scale voltage attacks and natural transients in FPGAs;word-length optimization beyond straight line code;word-length optimization beyond straight line code;embedding-based placement of processing element networks on FPGAs for physical model simulation;a remote memory access infrastructure for global address space programming models in FPGAs;architecture support for custom instructions with memory operations;high throughput and programmable online traffic classifier on FPGA;and indirect connection aware attraction for FPGA clustering.

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Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems 27

Inter-FPGA Routing Environment for Performance Exploration o...

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27th international symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Farooq, Umer Chotin-Avot, Roselyne Azeem, Moazam Ravoson, Maminionja Turki, Mariem Mehrez, Habib UPMC Univ Paris 06 Sorbonne Univ CNRS LIP6 Paris France

ISBN: (纸本)9781450345354

Multi-FPGA platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-FPGA based systems is severely affected by widening logic to I/O gap in FPGAs. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-FPGA based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-FPGA routing environment, effect of variation of number of FPGAs as well as number of inter-FPGA tracks on the performance of a target design is explored. For performance exploration and optimization, five different FPGA boards are utilized where number of FPGAs on board are varied from two to six. Moreover, for each board four different inter-FPGA track combinations are used. Experimental results reveal that multi-FPGA boards with inter-FPGA tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that FPGA board with six FPGAs gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four FPGAs gives better frequency-price tradeoff as compared to other FPGA boards under consideration.

关键词： field programmable gate arrays Routing Benchmark testing Computer architecture Program processors Target tracking Optimization

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2013年 iii页

作者： Hutchings, Brad Betz, Vaughn Brigham Young University United States University of Toronto Canada

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RapidSmith 2: A framework for BEL-level CAD exploration on Xilinx FPGAs 15

RapidSmith 2: A framework for BEL-level CAD exploration on X...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Haroldsen, Travis Nelson, Brent Hutchings, Brad Department of Electrical and Computer Engineering Brigham Young University ProvoUT84602 United States

ISBN: (纸本)9781450333153

RapidSmith is an open-source framework that allows for the exploration of novel approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor sup- port for manipulating designs below the slice level. In this paper, we highlight many of the projects RapidSmith en- ables and present extensions incorporated into "RapidSmith 2" that expose LUTs and ip-ops for direct manipulation in custom-built CAD tools. To demonstrate the utility of RapidSmith 2 we present the results of work to identify BELs in a design which must be clustered together and a tool that does pre-packing clustering accordingly. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

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49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design space exploration of L1 data caches for FPGA-based multiprocessor systems 15

Design space exploration of L1 data caches for FPGA-based mu...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Matthews, Eric Doyle, Nicholas C. Shannon, Lesley Simon Fraser University 8888 University Drive BurnabyBCV5A 1S6 Canada

ISBN: (纸本)9781450333153

Combining multi-processing with the high level of configurability possible with FPGA-based soft-processors, this paper presents a multiprocessing framework based on the MicroBlaze soft-processor that provides multicore support and fully coherent, independently configurable Level 1 Caches with Linux multicore support. This architecture allows for finegrain configurability of the system, allowing for FPGA resources to be better optimized for a specific embedded application. We use our framework to explore the L1 Data Cache configuration, developing a metric for efficiency based on resource usage and static application runtime. We find that a Pseudo-Random replacement policy is consistently the more efficient choice for FPGA systems.

关键词： field programmable gate arrays (FPGA)

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0.5-V highly power-efficient programmable logic using nonvolatile configuration switch in BEOL 15

0.5-V highly power-efficient programmable logic using nonvol...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Miyamura, Makoto Sakamoto, Toshitsugu Tsuji, Yukihide Tada, Munehiro Banno, Naoki Okamoto, Koichiro Iguchi, Noriyuki Hada, Hiromitsu West 7 16-1 Onogawa Tsukuba Ibaraki305-8569 Japan

ISBN: (纸本)9781450333153

A low-power nonvolatile programmable-logic cell array is proposed for energy-constrained applications such as wireless sensor nodes and mobile apparatuses. A 64 ×64 programmablelogic cell array includes a 9.2-Mbit nonvolatile switch, namely atom switch, as the routing switch and configuration memory. A 16-bit arithmetic logic unit, which is a building block of the micro-controller unit, was implemented to compare the speed and power consumption with a state-of-the-art low power fieldprogrammable gate array. The proposed programmable-logic array exhibited 30% dynamic power saving and x2.5 faster operation in the low-voltage region. Zero sleep power was also demonstrated.

关键词： Sensor nodes

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High-level design tools for floating point FPGAs 15

High-level design tools for floating point FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Singh, Deshanand P. Pasca, Bogdan Czajkowski, Tomasz S. Altera Corporation 150 Bloor Street West TorontoON Canada Altera Corporation Westwood High Wycombe BuckinghamshireHP12 4PU United Kingdom

ISBN: (纸本)9781450333153

This tutorial describes tools for efficiently implementing floating point applications on FPGAs. We present both the SDK for OpenCL and DSP Builder Advanced Blockset and show that they can be effectively used to implement many floating point applications. The methods for optimizing application performance are also described. In this tutorial we focus on a few applications, including Fast Fourier transform, matrix multiplication, finite impulse response filter and a Cholesky decomposition. In all cases we show what the tools are capable of achieving, and more importantly how a user can take advantage of the various floating-point centric features that are made available. We also discuss how these tools can automatically use FPGA architectural features such as hardened floating-point DSP available on Altera Arria 10 family. © Copyright 2015 acm.

关键词： field programmable gate arrays (FPGA)

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