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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 629 条记录，以下是11-20 订阅

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FRIDA: Reconfigurable arrays for Dynamically Scheduled High-Level Synthesis 25

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-...

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33rd acm/sigda international symposium on field-programmable gate arrays, FPGA 2025

作者： Coulon, Louis Ramirez, Lucas Anderson, Jason Stojilović, Mirjana Ienne, Paolo School of Computer and Communication Sciences EPFL Lausanne Switzerland Electrical and Computer Engineering Department University of Toronto Toronto Canada

ISBN: (纸本)9798400713965

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in contrast, provide ASIC-like performance but limited flexibility, typically supporting only feedforward programs with unambiguous memory accesses, far from the capabilities of HLS compilers. This work introduces a new class of reconfigurable arrays inspired by modern dynamically scheduled HLS (DHLS) tools. Unlike traditional HLS, DHLS compilers no longer produce explicit state machines, eliminating the need for look-up tables. Instead, they delegate scheduling decisions to a set of coarse-grained primitives. Our arrays leverage these primitives as processing elements and combine FPGA-style interconnect topology for high routing flexibility with CGRA-like bus-based interconnect. We present a framework to explore these arrays and evaluate a preliminary architecture using DHLS benchmarks. The results show an average of ∼2× speed improvement, but unfortunately only a ∼20% area reduction compared to an FPGA implemented on the same technology node. © 2025 Copyright held by the owner/author(s).

关键词： Program compilers

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Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine 24

Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Ray, Andy Devlin, Benjamin Quah, Fu Yong Yesantharao, Rahul Jane Street London United Kingdom Jane Street New York City United States

ISBN: (纸本)9798400704185

This paper presents a split CPU-FPGA Multi-Scalar Multiplication (MSM) engine written in Hardcaml. Hardcaml MSM was submitted to the 2022 ZPrize cryptography competition and won 1st place in the FPGA track. Hardcaml MSM targets the BLS12-377 elliptic curve and is currently the lowest-latency implementation utilizing FPGAs published. For a MSM of order 2^26 we achieve a single-round MSM latency of 5.518s and average power of 52W, with our design running at 278MHz. When performing multiple rounds of MSM with the same base points but random scalars, we are able to further mask host I/O and memory latency and reduce latency to 5.083s. This is a latency improvement of 13% over the previously fastest reported FPGA solution, and an improvement of 472% when compared to state of the art open-source CPU library gnark-crypto. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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Low-Latency, Line-Rate Variable-Length field Parsing for 100+ Gb/s Ethernet 24

Low-Latency, Line-Rate Variable-Length Field Parsing for 100...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Stitt, Greg Piard, Wesley Crary, Christopher University of Florida GainesvilleFL United States

ISBN: (纸本)9798400704185

field-programmable gate arrays (FPGAs) are widely employed in network-interface cards across applications including cloud services, machine learning, and high-frequency trading. These applications often share a common optimization goal: minimizing latency while meeting throughput constraints. In addition, these applications ideally aim to achieve "line-rate"operation, where the FPGA operates at full bandwidth without using back-pressure to stall incoming data. However, these goals are often conflicting. For example, to minimize latency, application protocols must effectively utilize network bandwidth by encoding variable-length data in variable-length fields. However, variable-length fields often have prohibitively complex processing requirements that prevent line-rate throughput or have excessive latency. In this paper, we present a novel variable-length field parser capable of scaling to accommodate the bus widths and clock frequencies necessary for 100+ Gb/s Ethernet, while still achieving low latency. Our experiments demonstrate parsing variable-length fields at line rate for anticipated bus widths and throughputs, achieving ultra-low latencies under 2 ns for some use cases. To the best of our knowledge, this latency surpasses existing work, including fixed-length field parsing. © 2024 acm.

关键词： Bandwidth

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FPGA Mux Usage and Routability Estimates without Explicit Routing 23

FPGA Mux Usage and Routability Estimates without Explicit Ro...

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31st acm/sigda international symposium on field programmable gate arrays (FPGA)

作者： Greene, Jonathan W. Univ Calif Berkeley Berkeley CA 94720 USA Cambios Comp LLC Berkeley CA 92121 USA

ISBN: (纸本)9781450394178

A new algorithm is proposed to rapidly evaluate an FPGA routing architecture without need of explicitly routing benchmark applications. The algorithm takes as input a probability distribution of nets to be accommodated and a description of an architecture. It produces an estimate for the usage of each type of mux in the FPGA (including intra-cluster muxes), valuable feedback to the architect. The estimates are shown to correlate with actual routed applications in both academic and commercial architectures. This is due in part to the algorithm's novel ability to account for long and multi-fanout nets. Run time is reduced by applying periodic graphs to model FPGAs' regular structure. We then show how Percolation Theory (a branch of statistical physics) can be applied to elucidate the relationship between mux usage and routability. We show that any blockages when routing a net are most likely to occur in the neighborhood of its terminals, and demonstrate a quantitative relationship among the post-placement wirelength of an application, the percolation threshold of an architecture, and the channel width required to map the application to the architecture. Supporting experimental data is provided.

关键词： FPGAs programmable routing percolation theory

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An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits 24

An FPGA-Enabled Framework for Rapid Automated Design of Phot...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Xu, Zhenyu Yu, Miaoxiang Cai, Jillian Gafsi, Saddam Ryckman, Judson Douglas Yang, Qing Wei, Tao University of Rhode Island KingstonRI United States Clemson University ClemsonSC United States

ISBN: (纸本)9798400704185

This paper introduces an FPGA-enabled framework to accelerate the automated design process for Photonic Integrated Circuit (PIC) devices. PICs are foreseen as a foundation for the next-generation semiconductors. However, the complexity of PIC design presents considerable challenges. Machine Learning (ML) techniques have shown promise in the realm of PIC design. The primary hurdle, however, is the extended training duration, solely constrained by the slow electromagnetic (EM) Finite-Difference Time-Domain (FDTD) solver. We propose a fast framework with a dedicated FPGA FDTD accelerator tailor-designed to speed up the PIC simulation. Benchmarking was carried out against commercial tools, with the single-FPGA accelerator outperforming both a multicore CPU and a GPU cluster. We taped out and evaluated the PIC devices designed through the proposed framework, and the experimental outcomes aligned. This demonstrates the full design circle, showcasing that the proposed framework enabled by FPGA breaks the current bottleneck in this domain. This study was conducted entirely on a commercial cloud platform (AWS), leveraging CPUs, FPGAs, and GPUs, with FPGA programming efficiently executed using High-Level Synthesis (HLS) and the Xilinx Runtime (XRT). The FPGA, along with its modern development tools, is seamlessly integrated into a heterogeneous computing platform, showcasing the accessible and practical nature of this approach. Our findings show the exciting possibility that ML-based physical design could be notably sped up enabled by FPGAs in a cloud-hosted heterogeneous cluster as a service. © 2024 acm.

关键词： field programmable gate arrays (FPGA)

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A Statically and Dynamically Scalable Soft GPGPU 24

A Statically and Dynamically Scalable Soft GPGPU

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Langhammer, Martin Constantinides, George A. Intel Corporation Imperial College London United Kingdom Imperial College London United Kingdom

ISBN: (纸本)9798400704185

Current soft processor architectures for FPGAs do not utilize the potential of the massive parallelism available. FPGAs now support many thousands of embedded floating point operators, and have similar computational densities to GPGPUs. Several soft GPGPU or SIMT processors have been published, but the reported large areas and modest Fmax makes their widespread use unlikely for commercial designs. In this paper we take an alternative approach, building the soft GPU microarchitecture around the FPGA resource mix available. We demonstrate a statically scalable soft GPGPU processor (where both parameters and feature set can be determined at configuration time) that always closes timing at the peak speed of the slowest embedded component in the FPGA (DSP or hard memory), with a completely unconstrained compile into a current Intel Agilex FPGA. We also show dynamic scalability, where a subset of the thread space can be specified on an instruction-by-instruction basis. For one example core type, we show a logic range - depending on the configuration - of 4k to 10k ALMs, along with 24 to 32 DSP Blocks, and 50 to 250 M20K memories. All of these instances close timing at 771 MHz, a performance level limited only by the DSP Blocks. We describe our methodology for reliably achieving this clock rate by matching the processor pipeline structure to the physical structure of the FPGA fabric. We also benchmark several algorithms across a range of data sizes, and compare to a commercial soft RISC processor. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs 24

REFINE: Runtime Execution Feedback for INcremental Evolution...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Park, Dongjoon Dehon, André University of Pennsylvania PhiladelphiaPA United States

ISBN: (纸本)9798400704185

FPGA design optimization is challenging for developers for two main reasons. First, developers cannot easily identify a bottleneck of the design to know where to focus optimization effort to improve the application execution time. Second, slow, monolithic FPGA compilation makes evaluation of each design change costly. Together, these make FPGA development different and more challenging than traditional software development where software engineers are accustomed to using rich profiling tools to improve their designs through a series of quick, incremental refinements. To address these issues, we propose a fast bottleneck identification scheme using runtime feedback and separate FPGA compilation. Our scheme systematically identifies bottlenecks in streaming computations based on FIFO event counters extracted from hardware execution and guides developers to the operations that limit performance. We showcase our support for bottleneck identification with the fast, automatic design space exploration, iterating initial design points quickly with a separate, incremental compilation strategy. When the design reaches the point that latency cannot improve with the separate compilation approach, we migrate to the monolithic design flow that does not have the area overhead and communication bandwidth limit of separate compilation approach. Then, the remaining design space, if any, is explored with a monolithic flow. When tested on the AMD ZCU102 embedded platform with realistic HLS dataflow designs, our approach correctly identifies bottlenecks improving application latency 2.2-12.7× while reducing tuning time by 1.3-2.7× compared to monolithic flow. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs 24

MiCache: An MSHR-inclusive Non-blocking Cache Design for FPG...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Xu, Shaoxian Lu, Sitong Shao, Zhiyuan Liao, Xiaofei Jin, Hai Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400704185

On FPGAs, customizing data parallelism can significantly improve performances of applications. However, a large number of applications, such as sparse matrix multiplication, exhibit irregular memory access patterns, for which further improvements are limited by their low memory access efficiency. It is challenging to solve using traditional caches due to the massive cache misses. To address this, prior research efforts are dedicated to developing non-blocking caches withMiss Status Holding Registers (MSHRs) to manage the cache misses and mitigate stalls caused by the misses. However, exsiting approaches allocate dedicatedBlock RAMs (BRAMs) for implementing MSHRs. It introduces complexities in MSHR configurations and potential resource inefficiencies, as MSHR demand is highly dynamic when solving real-world problems. In this paper, we present MiCache, an MSHR-inclusive non-blocking cache design where cache entries and MSHR entries share the same storage spaces to support the dynamic demand for MSHRs during the executions of applications. We design a consistent storage structure for cache and MSHR entries, ensuring a unified and efficient mechanism for cache/MSHR lookup and data access. To further improve the performance, we design a parallel dual pipeline, one of which processes the requests from processing elements, and the other processes the responses from off-chip memory. We implement and evaluate our proposal on a Xilinx Alveo U280 board. Evaluation results show that, compared to the state-of-the-art non-blocking cache design on FPGAs, with equivalent cache configurations, MiCache reduces the BRAM consumption by up to 17%. When using the same amount of BRAM resources, MiCache achieves up to 1.56x performance improvement. © 2024 acm.

关键词： field programmable gate arrays (FPGA)

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SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC 24

SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Lin, Will Shan, Yizhou Kosta, Ryan Krishnamurthy, Arvind Zhang, Yiying University of California San Diego San DiegoCA United States University of Washington Seattle WA United States

ISBN: (纸本)9798400704185

With CPU scaling slowing down in today's data centers, more functionalities are being offloaded from the CPU to auxiliary devices. One such device is the SmartNIC, which is being increasingly adopted in data centers. In today's cloud environment, VMs on the same server can each have their own network computation (or network tasks) or workflows of network tasks to offload to a SmartNIC. These network tasks can be dynamically added/removed as VMs come and go and can be shared across VMs. Such dynamism demands that a SmartNIC not only schedules and processes packets but also manages and executes offloaded network tasks for different users. Although software solutions like an OS exist for managing software-based network tasks, such software-based SmartNICs cannot keep up with the quickly increasing data-center network speed. This paper proposes a new SmartNIC platform called SuperNIC that allows multiple tenants to efficiently and safely offload FPGA-based network computation DAGs. For efficiency and scalability, our core idea is to group network tasks into virtual chains that are dynamically mapped to different forms of physical chains depending on load and FPGA space availability. We further propose techniques to automatically scale network task chains with different types of parallelism. Moreover, we propose a fair sharing mechanism that considers both fair space sharing and fair time sharing of different types of hardware resources. Our FPGA prototype of SuperNIC achieves high bandwidth and low latency performance whilst efficiently utilizing and fairly sharing resources. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network 24

GraFlex: Flexible Graph Processing on FPGAs through Customiz...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Su, Chunyou Du, Linfeng Liang, Tingyuan Lin, Zhe Wang, Maolin Sinha, Sharad Zhang, Wei The Hong Kong University of Science and Technology Kowloon Hong Kong Sun Yat-sen University Guangdong ShenZhen China New Territories Hong Kong Indian Institute of Technology Goa Goa India

ISBN: (纸本)9798400704185

Graph processing system design has been widely considered to be a challenging topic due to the mismatch between the computational throughput requirement and the memory bandwidth. Recent works try to deliver better graph processing systems by taking advantage of application-specific architectures and emerging high-bandwidth memory on FPGAs. However, there is still ample room for improvements regarding flexibility, scalability, and usability. This paper presents GraFlex, a flexible scatter-gather graph processing framework on FPGAs with scalable interconnection networks. It adopts the Bulk-Synchronous Parallel (BSP) paradigm for global control and synchronization, enabling rapid deployment of performant graph processing systems through HLS-based design flows. GraFlex conducts software-hardware co-optimization to boost system performance. It configures the compact graph format, partition scheme, and memory channel allocation strategy to support scalable designs. Resource-efficient multi-stage butterfly interconnection network achieves on-device data communication and facilitates throughput matching. To handle fragmented memory requests, we propose coalesced memory access engines to improve bandwidth utilization. GraFlex is comprehensively evaluated with various graph applications and real-world datasets. Our results show up to 2.09\texttimes average speedup in traversal throughput over the existing state-of-the-art work with a non-negligible reduction in power and resource consumption. A case study of the breadth-first search (BFS) application shows a 6.58\texttimes speedup in average algorithm throughout with proper implementation choices enabled by the scatter-gather mechanism implemented. The BFS study also reports an almost linear throughput scaling versus the number of processing elements (PEs) and memory channels. © 2024 acm.

关键词： field programmable gate arrays (FPGA)

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