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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是201-210 订阅

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An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation 1

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IFIP/IEEE WG 10.5 21st international Conference on Very Large Scale Integration (VLSI-SoC)

作者： Papadimitriou, Kyprianos Thomas, Sotiris Dollas, Apostolos Tech Univ Crete Akrotiri Sch ECE Khania 73100 Greece

ISBN: (数字)9783319237992

ISBN: (纸本)9783319237992

The implementation of 3D stereo matching in real time is an important problem for many vision applications and algorithms. The current work, extending previous results by the same authors, presents in detail an architecture which combines the methods of Absolute Differences, Census, and Belief Propagation in an integrated architecture suitable for implementation with field programmable gate Array (FPGA) logic. Emphasis on the present work is placed on the justification of dimensioning the system, as well as detailed design and testing information for a fully placed and routed design to process 87 frames per sec (fps) in 1920 x 1200 resolution, and a fully implemented design for 400 x 320 which runs up to 1570 fps.

关键词： Stereo matching Correspondence problem Real-time field programmable gate arrays Absolute differences Census Belief propagation

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A cost-effective way to expand the scope of FPGA based projects 10

A cost-effective way to expand the scope of FPGA based proje...

引用

10th IEEE international Conference on Microelectronics Systems Education, MSE 2015

作者： Chu, Pong P. Department of Electrical and Computer Engineering Cleveland State University ClevelandOH4115 United States

ISBN: (纸本)9781479999132

FPGA is widely used in Computer Engineering and related curricula. However, most lab exercises are performed and constrained largely in a self-contained FPGA board. A serial interface is a simple, cost-effective way to connect FPGA board to outside systems. It can be used to control a robot platform, to communicate with desktop computers, to interact with Android devices, to establish a ZigBee wireless link, and to connect to internet. This greatly expands the scope of FPGA based experiments and projects and makes them more interesting and versatile. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA based Random Waveform Generators for Noise Radars 16

FPGA based Random Waveform Generators for Noise Radars

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16th international Radar symposium (IRS)

作者： Lukin, Sergiy Zemlyaniy, Oleg Lukin, Konstantin NAS Ukraine Usikov Inst Radiophys & Elect LNDES 12 Proskura St UA-61085 Kharkov Ukraine

ISBN: (纸本)9783954048533

The results on the use of arbitrary waveform generators that are based on FPGA technology for generation of complex signals in modern noise radars are presented. On the basis of these devices we propose a radar scheme with digital generation of noise waveforms for both sounding signal and reference and analog processing (stepped-delay method for noise radar). Experimental testing shows efficiency of FPGA-based application in radar with variety of sounding waveforms.

关键词： waveform generators field programmable gate arrays noise radar audio signals radar complex signal Noise waveforms analog processing

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Efficient Architecture and Implementation for NTRUEncrypt System 58

Efficient Architecture and Implementation for NTRUEncrypt Sy...

引用

IEEE 58th international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Liu, Bingxin Wu, Huapeng Univ Windsor Elect & Comp Engn Windsor ON N9B 3P4 Canada

ISBN: (纸本)9781467365574

NTRU has gained much attention recently because it is relatively efficient for practical implementation among the post-quantum public key cryptosystems. In this paper, an efficient hardware architecture and FPGA implementation of NTRUEncrypt is proposed. The new architecture takes advantage of linear feedback shift register (LFSR) structure for its compact circuitry and high speed. A novel design of the modular arithmetic unit is proposed to reduce the critical path delay. The FPGA implementation results have shown that the proposed design outperforms all the existing works in terms of area-delay product.

关键词： field programmable gate arrays (FPGA)

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Accelerating machine learning kernel in hadoop using FPGAs 15

Accelerating machine learning kernel in hadoop using FPGAs

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15th IEEE/acm international symposium on Cluster, Cloud, and Grid Computing, CCGrid 2015

作者： Neshatpour, Katayoun Malik, Maria Homayoun, Houman Department of Electrical and Computer Engineering George Mason University United States

ISBN: (纸本)9781479980062

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. % Considering the time dedicated to create such specialized architectures, a model that estimates the potential speedup achievable through offloading various parts of the algorithm to specialized hardware would be necessary. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Signboards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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The Use of FPGA Evaluation Board as Data Acquisition and Pre-processing System for Synthetic Aperture Radar 16

The Use of FPGA Evaluation Board as Data Acquisition and Pre...

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16th international Radar symposium (IRS)

作者： Drozdowicz, Jedrzej Samczynski, Piotr Wielgo, Maciej Gromek, Damian Klincewicz, Karol Warsaw Univ Technol Inst Elect Syst Warsaw Poland

ISBN: (纸本)9783954048533

Experiments on Synthetic Aperture Radar require a data acquisition and storage system. Custom-made systems are well suited to this specific application, but the development of such a system is both time and resource consuming. The use of an off-the-shelf FPGA evaluation board with interchangeable analogue to digital converter cards as a data acquisition and pre-processing system was proposed. Such an approach allows not only for operation with different analogue front-ends, but also for the implementation of data pre-processing, such as modulation and decimation. The modulation makes further processing easier and the filtration-decimation reduces the size of the data stream. A complete system was tested thoroughly during a ground-based experiment and is now ready for airborne testing. As there are unused resources in the FPGA, they will be utilized in the future for the implementation of real-time processing.

关键词： Data Collection Methods Synthetic aperture radar field programmable gate arrays analog digital converter real-time process dimensional data Board Pretreatment

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SNNAP: Approximate Computing on programmable SoCs via Neural Acceleration 21

SNNAP: Approximate Computing on Programmable SoCs via Neural...

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IEEE 21st international symposium on High Performance Computer Architecture (HPA)

作者： Moreau, Thierry Wyse, Mark Nelson, Jacob Sampson, Adrian Esmaeilzadeh, Hadi Ceze, Luis Oskin, Mark Univ Washington Seattle WA 98195 USA Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781479989300

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs. We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current "C-to-gates" high-level synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8xspeedup (as high as 38.1x) and 2.8x energy savings (as high as 28x) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

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Time Synchronization for Real-time Control Systems without PTP-enabled Switches 9

Time Synchronization for Real-time Control Systems without P...

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international IEEE symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS ) proceedings

作者： Maruyama, Tatsuya Yamada, Tsutomu Yoshida, Shouji Kido, Mitsuyasu Komatsu, Chikashi Hitachi Ltd Res & Dev Grp Ctr Technol Innovat Energy 1-1 Omika Cho 7 Chome Hitachi Ibaraki 3191292 Japan Hitachi Ltd Infrastruct Syst Co Hitachi Ibaraki 3191293 Japan

ISBN: (纸本)9781467375955

IEEE 1588 is a promising way of time synchronization in control systems that include IT. Intermediate devices such as network switches are needed when the control systems are built on a multi-hop network for wide area operations. However, the introduction of switches causes conflicts between the reply packets from the devices in a switch, and thus, the delays on the backward and forward paths would be different and the synchronization accuracy is degraded as a result. On the other hand, it is difficult to build low cost control systems when using dedicated switches for the precision time protocol (i.e., boundary clock or transparent clock). Therefore, the authors propose a method that estimates the conflicts between synchronization packets based on the observable information by using the synchronization master device and applies the estimation to the synchronization method. We used communication evaluation board to create a prototype for the proposed method and then evaluated it. The results showed that the level of accuracy was +/- 1 mu s accuracy under five slaves and that there was a 2-msec cyclic time synchronization.

关键词： IEEE standards frequency hop communication protocols synchronisation IEEE 1588 boundary clock multi-hop network precision time protocol real-time control systems time synchronization transparent clock wide area operations Accuracy field programmable gate arrays Lead Ports (Computers) Switches Synchronization clock recovery Switches wireless multi-hop networks field programmable gate arrays frequency hop communication real-time control system control systems protocols IEEE Standards Lead

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Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras 1

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22nd IFIP WG 10.5/IEEE international Conference on Very Large Scale Integration (VLSI-SoC)

作者： Seyid, Kerem Cogal, Oemer Popovic, Vladan Afshari, Hossein Schmid, Alexandre Leblebici, Yusuf Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (数字)9783319252797

ISBN: (纸本)9783319252797

The Panoptic camera is an omnidirectional multi-aperture visual system which is realized by mounting multiple imaging sensors on a hemispherical frame. In this chapter, we will present a novel distributed and parallel implementation of the real-time omnidirectional vision reconstruction algorithm of the Panoptic Camera, for camera modules with processing, memory and interconnectivity features. A methodology for the arrangement of camera modules with interconnectivity feature into a target interconnection network topology will be introduced. A unique custom-made multiple-FPGA hardware platform designed for the implementation of an interconnected network of a 49 camera prototype Panoptic system will be explained. A novel way to represent the omnidirectional data obtained from the Panoptic Camera and real-time high dynamic range (HDR) video application which is realized by the system will be presented.

关键词： field programmable gate arrays Smart cameras Real-time systems Omnidirectional imaging Telepresence High dynamic range

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Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform 15

Architecting to Achieve a Billion Requests Per Second Throug...

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acm/IEEE 42nd Annual international symposium on Computer Architecture (ISCA)

作者： Li, Sheng Lim, Hyeontaek Lee, Victor W. Ahn, Jung Ho Kalia, Anuj Kaminsky, Michael Andersen, David G. Seongil, O. Lee, Sukhan Dubey, Pradeep Intel Labs Santa Clara CA 95054 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Seoul Natl Univ Seoul 151 South Korea

ISBN: (纸本)9781450334020

Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency control. Two recent research thrusts have focused upon improving key-value performance. Hardware-centric research has started to explore specialized platforms including FPGA5 for KVSs;results demonstrated an order of magnitude increase in throughput and energy efficiency over stock memcached. Software-centric research revisited the KVS application to address fundamental software bottlenecks and to exploit the full potential of modern commodity hardware;these efforts too showed orders of magnitude improvement over stock memcached. We aim at architecting high performance and efficient KVS platforms, and start with a rigorous architectural characterization across system stacks over a collection of representative KVS implementations. Our detailed full-system characterization not only identifies the critical hardware/software ingredients for high-petformance KVS systems, but also leads to guided optimizations atop a recent design to achieve a record setting throughput of 120 million requests per second (MRPS) on a single commodity server. Our implementation delivers 9.2X the performance (RPS) and 2.8X the system energy efficiency (RPS/watt) of the best-published FPGA-based claims. We craft a set of design principles for future platform architectures, and via detailed simulations demonstrate the capability of achieving a billion RPS with a single server constructed following our principles.

关键词： field programmable gate arrays (FPGA)

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