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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是211-220 订阅

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FPGA-based Network-Resonance Applebaum Adaptive arrays for Directional Spectrum Sensing 58

FPGA-based Network-Resonance Applebaum Adaptive Arrays for D...

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IEEE 58th international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Udayanga, Nilan Madanayake, Arjuna Wijenayake, Chamith Univ Akron Dept Elect & Comp Engn Akron OH 44325 USA Univ New S Wales Sch Elect Engn & Telecom Sydney NSW 2052 Australia

ISBN: (纸本)9781467365574

Cognitive radio (CR) depends on the accurate detection of frequency, modulation, and direction pertaining to radio sources, in turn, leading to spatio-temporal directional spectrum sensing. False detections due to high levels of noise and interference may adversely impacts the CR's performance. To address this problem, a novel system architecture that increases the accuracy of directional spectrum sensing in situations with low signal to noise ratio (SNR) is proposed. This work combines adaptive arrays, multidimensional filter theory and cyclostationary feature detection. A linear array Applebaum beamformer is employed in conjunction with a two-dimensional (2-D) planar-resonant beam filter to perform highly directional receive mode wideband beamforming with improved spatial selectivity. A Xilinx Virtex-6 based field programmable gate array (FPGA) prototype of the improved beamforming front-end verifies a clock frequency of 100.9 MHz. The proposed network-resonant Applebaum array provides 6 dB, 5.5 dB and 5 dB noise suppression capability reflected in the spectral correlation function for input SNRs of -20 dB, -25 dB, and -30 dB, respectively, for an RF beam direction 50. degrees from array broadside.

关键词： Cognitive radio

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An FPGA Based Passive K-Delta-1-Sigma Modulator 58

An FPGA Based Passive K-Delta-1-Sigma Modulator

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IEEE 58th international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Roy, Angsuman Meza, Matthew Yurgelon, Joey Baker, R. Jacob Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA

ISBN: (纸本)9781467365574

An FPGA based 2nd-order passive KD1S sigma-delta modulator was designed, simulated and tested. The design is implemented on an Altera Cyclone IV EP4CE115 FPGA. All active components such as digital logic, clock circuitry, and registers are located internally on the FPGA chip with only passive RC lumped analog components located off chip. The circuit uses eight logic elements and two PLL blocks on the FPGA to create an eight path KD1S sigma-delta modulator. The design performance was quantified at effective sampling rates of 80 MHz and 450 MHz. The implementation achieved a peak SNR of 58 dB and an ENOB of 9.3 bits at a 450 MHz effective sampling rate. The key benefit of this approach is the absence of active analog components, very low power, and high-speed sampling.

关键词： field programmable gate arrays design performance delta modulator Delta sigma modulation Registers Modulators

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Demonstration of an FPGA Controller for Guaranteed-Rate Optical Packet Switching 14

Demonstration of an FPGA Controller for Guaranteed-Rate Opti...

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IFIP/IEEE international symposium on Integrated Network Management (IM)

作者： Rezaee, Maryam Szymanski, Ted H. McMaster Univ Dept ECE Hamilton ON Canada

ISBN: (纸本)9783901882760

A switch controller which achieves low-latency deterministic 'Guaranteed-Rate' (GR) connections in packet switched networks is demonstrated on a 'field programmable gate Array' (FPGA) device. A Software Defined Networking (SDN) control plane can configure the FPGA controllers to establish deterministic GR connections in a forwarding plane of IP routers or layer-2 packet switches. The use of deterministic GR connections can reduce queueing delays to negligible values, so that the end-to-end delays are reduced to the fiber latency. The switch controller can operate routers, switches and links at 100% loads, while simultaneously guaranteeing very low end-to-end queueing delays. A testbed consisting of 8 switches in a linear array is synthesized on an Altera Cyclone IV FPGA. An SDN control plane routes 128 traffic flows through the testbed to saturate the switches and links. Packets move through the forwarding plane at a clock rate of 52 MHz, transferring millions of packets per second, and statistics are recorded. The demonstration shows that all traffic flows in the testbed achieve deterministic GR service. The FPGA demonstration is accompanied by a video which visually illustrates packet forwarding in the network. The GR technology applies to IP routers and layer 2 packet switched networks, with thousands of nodes spanning arbitrary distances. The FPGA controller also applies to layer 2 MPLS (Multiprotocol Label Switching) and Ethernet switches, and to 'Optical Packet Switched' networks, to achieve deterministic GR services and to operate links at 100% loads.

关键词： field programmable gate arrays IP Router Packet Packet switched networks Switches clock frequency deterministic Controllers layer 2

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FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration 23

FAME: A Fast and Accurate Memory Emulator for New Memory Sys...

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23rd international symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Malladi, Krishna T. Chang, Mu-Tien Ping, John Zheng, Hongzhong Samsung Semicond Inc Memory Solut Lab San Jose CA 95134 USA

ISBN: (纸本)9781467377201

Memory systems are critical to system responsiveness and operating costs. New memory technologies like PCM, STT-MRAM, RRAM are poised to provide an intermediate memory layer between DRAM and flash to better serve the needs of capacity, latency hungry datacenter applications. To drive their efficient deployment, it is imperative to make complex architectural decisions and justify the need to rethink system design. To assist this, we present FAME: a Fast and Accurate Memory Emulator methodology that combines the speed and accuracy of emulation with the detail of simulation for memory systems. We use QPI FPGA that is mainly used to accelerate computations, in a novel way to bring fast, cache-coherent DRAM emulation to systems that relied only on limited capabilities of simulation and NUMA platforms. Furthermore, we describe an integrated methodology that helps navigate DRAM memory caching and new technologies' microarchitectural timing simulation. Using FAME, we demonstrate that applications could obtain upto 2-3x system speedup using the new memory system tier.

关键词： Bandwidth Benchmark testing Emulation field programmable gate arrays Microarchitecture Random access memory Timing

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Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

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FPGA'12 - proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

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2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy FPGA-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on FPGA;incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on FPGAs;saturating the transceiver bandwidth: switch fabric design on FPGAs;limit study of energy & delay benefits of component-specific routing;impact of FPGA architecture on resource sharing in high-level synthesis;and securing netlist-level FPGA design through exploiting process variation and degradation.

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Hardware Accelerated Flow Measurement of 100 Gb Ethernet 14

Hardware Accelerated Flow Measurement of 100 Gb Ethernet

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IFIP/IEEE international symposium on Integrated Network Management (IM)

作者： Pus, Viktor Velan, Petr Kekely, Lukas Korenek, Jan Minarik, Pavel CESNET Zspo Zikova 4 Prague 16000 Czech Republic INVEA TECH As Brno 61600 Czech Republic

ISBN: (纸本)9783901882760

This demo demonstrates results of a joint research project of CESNET and INVEA-TECH focused on 100 GbE network flow monitoring using FPGA. It shows, to the best of our knowledge, the first flow monitoring setup capable of handling fully saturated 100G Ethernet line. We present COMBO-CG card that provides accurate timestamps for high-resolution traffic monitoring. The card is complemented by fast DMA engine and optimized Linux drivers which were designed and implemented to achieve 100 Gbps data transfers through PCIe bus with low CPU utilization. Network traffic can be distributed among multiple CPU cores based on configurable hash functions. Our flow exporter is able to fully utilize available CPU cores to provide wire-speed performance for processing of the 100 Gbps traffic. The demo will show complete 100G flow monitoring setup from packet generator to flow collector.

关键词： research project Flow measurement FLOW MONITOR central processing units Accelerated flow Gbps field programmable gate arrays speed performance

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Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 Compatibility 27

Single-Loop Approach to 2-D Wavelet Lifting with JPEG 2000 C...

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IEEE 27th international symposium on Computer Architecture and High Performance Computing

作者： Barina, David Musil, Petr Musil, Martin Zemcik, Pavel Brno Univ Technol CS-61090 Brno Czech Republic

ISBN: (纸本)9781467386210

A novel approach to 2-D single-loop wavelet lifting with compatibility to JPEG 2000 is presented in this paper. A newly developed 2-D core of CDF 5/3 wavelet filter is presented that, using a new sequence of operations, simplify the design. Moreover, the proposed approach, that uses one pass for 2-D transform, directly produces final output and reduces significantly the need for storing intermediate results into memory. All the proposed structures can be efficiently pipelined in hardware. This paper describes the proposed approach, its implementation in FPGA, cost of such implementation, and brings an experimental evaluation as well as discussion of the features of the approach.

关键词： Discrete wavelet transforms field programmable gate arrays

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SAT solving using FPGA-based heterogeneous computing 15

SAT solving using FPGA-based heterogeneous computing

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IEEE international Conference on Computer-Aided Design

作者： Jason Thong Nicola Nicolici Department of Electrical and Computer Engineering McMaster University

ISBN: (纸本)9781467383899

We present a heterogeneous computing solution to the Boolean satisfiability (SAT) problem. Our field-programmable gate array (FPGA)-based implementation for accelerating the common case computation within a SAT solver utilizes most of the FPGA resources and it seamlessly integrates with our software host. Algorithms and data structures were redesigned to maximize the strengths of customized computing and generalizable optimizations are proposed to maximize throughput, minimize communication latencies, and compact hardware memory. We are significantly faster than state-of-the-art SAT solvers in software and hardware.

关键词： Hardware field programmable gate arrays Instruction sets Layout Multithreading

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