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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Hardware implementation of all digital calibration for undersampling TIADCs

Hardware implementation of all digital calibration for under...

引用

IEEE international symposium on Circuits and Systems, ISCAS 2015

作者： Le Duc, Han Nguyen, Duc Minh Jabbour, Chadi Graba, Tarik Desgreys, Patricia Jamin, Olivier Nguyen, Van Tam Institut Mines-Télécom Télécom ParisTech CNRS LTCI 46 Rue Barrault Paris75013 France NXP Semiconductors 2 Esplanade Anton Phillips Caen14000 France Department of EECS University of California at Berkeley CA94720 United States

ISBN: (纸本)9781479983919

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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An Architecture for Configuring an Effcient Scan Path for a Subset of Elements 29

An Architecture for Configuring an Effcient Scan Path for a ...

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29th IEEE international Parallel and Distributed Processing symposium Workshops, IPDPSW 2015

作者： Ashrafi, Arash Vaidyanathan, Ramachandran Division of Electrical and Computer Engineering Louisiana State University Raton RougeLA United States

ISBN: (纸本)0769555101

Many FPGAs support partial reconfiguration, where the states of a subset of configurable elements is (potentially) altered. However, the configuration bits often enter the chip through a small number of pins. Thus, the time needed to partially reconfigure an FPGA depends, to a large extent, on the number of configuration bits to be input into the chip. This is a key consideration, particularly where partial reconfiguration is performed during the computation. Therefore, it is important that the size of a frame (an atomic configuration unit) be small and the configuration be focused on the bits that truly need to be altered. Suppose ℂ denotes the set of elements that need to be configured during a partial reconfiguration phase, here ℂ is a (small) subset of k frames from a much larger set S of n frames. In this paper we present a method to configure the k elements of ℂ by setting up a configuration path that strings its way through only those frames that require reconfiguration, the configuration bit stream can be now shifted in through this path. Our method also automatically selects (in hardware) a suitable clock speed that can be used to input these configuration bits. If the elements of ℂ show spatial locality, then the configuration time could be made largely independent of n. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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Analyzing the Impact of X-ray Tomography on the Reliability of Integrated Circuits 41

Analyzing the Impact of X-ray Tomography on the Reliability ...

引用

41st international symposium for Testing and Failure Analysis (ISTFA 2015)

作者： Dogan, Halit Alam, Md Mahbub Asadizanjani, Navid Shahbazmohamadi, Sina Forte, Domenic Tehranipoor, Mark Univ Connecticut Elect & Comp Engn Storrs CT USA Manhattan Coll Mech Engn Riverdale NY USA Univ Florida Elect & Comp Engn Gainesville FL USA

ISBN: (纸本)9781627081023;9781627081030

X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major fmding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

关键词： field programmable gate arrays (FPGA)

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Logic gates in the routing network of FPGAs (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of FPGA architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

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6/12-channel synchronous digital phasemeter for ultrastable signal characterization and use

6/12-channel synchronous digital phasemeter for ultrastable ...

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2015 Joint Conference of the IEEE international Frequency Control symposium and the European Frequency and Time Forum, FCS 2015

作者： Massimo, Caligaris Costanzo, Giovanni A. Calosso, Claudio E. Department of Electronics and Telecommunication Politecnico di Torino Torino Italy Istituto Nationale di Ricerca Metrologica INRIM Torino Italy INRIM Politecnico di Torino Torino Italy

ISBN: (纸本)9781479988662

Nowadays, in primary time and frequency laboratories we can find high spectral purity signals in the 10 MHz - 10 GHz range generated from cryogenic oscillators or ultra-stable lasers together with frequency combs. Their short-term stability surpasses by one to two orders of magnitude the performances of active hydrogen masers (AHM), while in the long-term AHMs still have a better behavior. The new technology can be considered mature for what concern spectral purity, but we cannot say the same about complexity, power consumption and reliability. In this sense, it is important to measure ultra-stable sources with respect to AHMs. First, to test their spectral purity or, at least, to give it an upper bound;second to have a continuous monitoring;finally, to combine them in order to get the best of all in term of phase noise and frequency stability. All of these requirements can be satisfied by the system we are developing. It is a multi-channel synchronous and real-time phasemeter based on Tracking Direct Digital Synthesizer (TDDS) technique. The results related to the first prototype are presented. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs 15

Redundancy based interconnect duplication to mitigate soft e...

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IEEE international Conference on Computer-Aided Design

作者： Naifeng Jing Jiacheng Zhou Jianfei Jiang Xin Chen Weifeng He Zhigang Mao Department of Micro-Nano Electronics Shanghai Jiao Tong University Shanghai China School of Electronics and Information Engineering Tongji University Shanghai China

ISBN: (纸本)9781467383899

Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (field programmable gate arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the configuration bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable configuration bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

关键词： Circuit faults field programmable gate arrays Routing Integrated circuit interconnections Switches Wires Table lookup

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Hardware accelerator design for data centers 15

Hardware accelerator design for data centers

引用

IEEE international Conference on Computer-Aided Design

作者： Serif Yesil Muhammet Mustafa Ozdal Taemin Kim Andrey Ayupov Steven Burns Ozcan Ozturk Intel Corp Santa Clara CA US Intel Corp Bilkent Univ Ankara Turkey

ISBN: (纸本)9781467383899

As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs.

关键词： field programmable gate arrays Acceleration Graphics processing units Big data Libraries Hardware

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An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD 45

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMD...

引用

45th IEEE international symposium on Multiple-Valued Logic, ISMVL 2015

作者： Nakahara, Hiroki Sasao, Tsutomu Nakanishi, Hiroyuki Iwai, Kazumasa Ehime University 3 Chome Matsuyama Ehime790-8577 Japan Meiji University Kawasaki Kanagawa214-8571 Japan Kagoshima University 1-21-40 Korimoto Kagoshima890-0065 Japan Nobeyama Radio Observatory Minamimaki Minamisaku Nagano384-1305 Japan

ISBN: (纸本)9781479917778

This paper proposes an FFT circuit based on aresidue number system (RNS) using LUT cascades. To reduce the number of look-up tables (LUTs) in an FPGA, we usedtwo techniques. The first one is the functional decomposition of multipliers using RNS. The second one is the increase of the dynamic range stage by stage. The circuit requires the RNS2RNSconverter which converts a small dynamic range to a large dynamic range. To compactly realize the RNS2RNS converter, we decompose it into an RNS2Binary converter and a Binary2RNSconverter. Although the Binary2RNS converter can be realized by an LUT cascade based on a multi-terminal multi-valued decision diagram (MTMDD), the RNS2Binary converter tend tube large for the conventional circuit. Thus, we introduce an LUTcascade based on a modulo edge-valued multi-valued decision diagram (mod-EVMDD). The mod-EVMDD is a new type of a decision diagram that efficiently represents the RNS2Binaryconverter. We implemented the proposed RNS FFT on the Xilinx Corp. Virtex 6 FPGA. Compared with the conventional binary FFT implementation, although the number of blockRAMs (BRAMs) increased by 11.1-25.0%, the number of LUTsdecreased by 44.2-52.2% and the maximum clock frequency increased by 9.3-41.7%. With this technique, we successfully implemented a required FFT on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only) 15

FiT: An Automated Toolkit for Matching Processor Architectur...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Charles Mutigwe Johnson Kinyua Farhad Aghdasi NxCORES Research East Longmeadow MA USA Virginia International University Fairfax VA USA University of Fort Hare Alice South Africa

ISBN: (纸本)9781450333153

As the complexity of designing electronic systems continues to grow, the most commonly used solution has been to move the design process to higher levels of abstraction via software tools. In this work we present one such tool that can be used to automatically generate custom processors and systems-on-chip (SoC) from C source code or application binary files, with no requirement for the user to understand any of the underlying hardware systems. This tool also does not call for the application to be profiled for any 'hot spots' as a prerequisite for generating the custom processor. We use the toolkit to generate two types of custom processors; the area-optimized processors and the performance-optimized processors. We study the resource utilization of the custom processors and compare them with those predicted by the core density model. We find that the performance-optimized processor results are as predicted by the core density model.

关键词： electronic system level (esl) design application-specific soft processor reconfigurable computing c-to-silicon compiler

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A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only) 15

A Mixed-Grained Reconfigurable Computing Platform for Multip...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Leibo Liu Yingjie Chen Dong Wang Min Zhu Shouyi Yin Shaojun Wei Tsinghua University Beijing China Beijing Jiaotong University Beijing China

ISBN: (纸本)9781450333153

A mixed-grained reconfigurable computing platform targeting multiple-standard video decoding is proposed in this paper. The platform integrates eight coarse-grained Reconfigurable Processing Units (RPUs), each of which consists of 16×16 multi-functional Processing Elements (PEs) and are implemented in TSMC 65 nm technology and two Altera Stratix IV EP4SE820 FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including H.264, MPEG-2, AVS and HEVC. Two types of platform configuration are tested in this work. One configuration utilizes two RPUs and targets multiple-standard high-definition (HD) video decoding, while the other utilizes only one RPU, which works under a lower frequency and targets at standard resolution (SD) decoding. The HD configuration can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz and 1920×1080 HEVC video streams at 30 fps under 236 MHz. It achieves a 25% performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 3.85× performance boosts over the Intel i5 general-purpose CPU for HEVC decoding.

关键词： field-programmable gate array coarse-grained reconfigurable array video decoding reconfigurable computing

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