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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是231-240 订阅

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Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only) 15

Architecture of Reconfigurable-Logic Cell Array with Atom Sw...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Xu Bai Yukihide Tsuji Ayuka Morioka Makoto Miyamura Toshi Sakamoto Munehiro Tada Naoki Banno Koichiro Okamoto Noriyuki Iguchi Hiromitsu Hada Low-power Electronics Association & Project (LEAP) Tsukuba Japan

ISBN: (纸本)9781450333153

Emerging nonvolatile memories (NVMs) have a potential to overcome the issues in the conventional static random-access memory (SRAM) based reconfigurable logic cell arrays (RLCAs). Replacing a CMOS switch element composed of a SRAM and a pass transistor by a NVM reduces chip size. And non-volatility reduces the stand-by power. More importantly, the compactness of NVM allows fine-grain logic cells (small cluster size), which advantageously enables a highly efficient cell usage, resulting in compact circuit for applications. In this paper, we investigate the fine-grain cell architecture using atom switch which is one of the NVMs. We evaluate the effect of the cluster size and the segment length on the atom-switch-based RLCA to confirm the optimal point considering area-delay product. Cluster size is optimized to be 4, which is smaller than that in the conventional SRAM- and multiplexer-based RLCA. This optimization is originated from the fact that the inter-delay among clusters is only twice of the intra-delay in cluster for atom-switch-based RLCA with routing block formed by crossbar switches because of very small capacitance and resistance of atom switches. On the other hand, the segment length is optimized to be 4, which is the same as that in the conventional SRAM- and multiplexer-based RLCA.

关键词： programmable logic routing fabrics cross bar switch atom switch cluster nonvolatile

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Computation-in-memory based parallel adder

Computation-in-memory based parallel adder

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IEEE international symposium on Nanoscale Architectures (NANOARCH)

作者： Hoang Anh Du Nguyen Lei Xie Mottaqiallah Taouil Razvan Nane Said Hamdioui Koen Bertels Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft Zuid-Holland NL Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft CD The Netherlands

Today's computing systems suffer from memory/communication bottleneck, resulting in energy and performance inefficiency. This makes them incapable to solve data-intensive applications within economically acceptable limits. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor technology offers a potential solution for the memory bottleneck. This paper presents a CIM based parallel adder, and shows its potentials and superiority for intensive computing and massive parallelism by comparing it with state-of-the art computing systems including multicore, GPU and FPGA architecture. The results show that CIM based parallel adder can achieve at least two orders of magnitude improvement in computational efficiency, energy efficiency and area efficiency.

关键词： Adders Computer integrated manufacturing Graphics processing units Multicore processing field programmable gate arrays Delays

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Threshold logic synthesis based on cut pruning 15

Threshold logic synthesis based on cut pruning

引用

IEEE international Conference on Computer-Aided Design

作者： Augusto Neutzling Jody Maick Matos Andre I. Reis Renato P. Ribas Alan Mishchenko Institute of Informatics Federal University of Rio Grande do Sul Brazil Department of EECS University of California Berkeley

ISBN: (纸本)9781467383899

This paper presents a novel approach to synthesize circuits based on threshold logic gates (TLGs). Emerging technologies, such as memristors, spintronics devices and tunneling diodes, are able to build this class of gates efficiently. For this reason, threshold logic is a promising alternative to conventional CMOS logic. The proposed approach is based on pruning non-threshold-logic cuts in order to limit the search space during technology mapping. As a result, both the number of TLGs and logic depth of the synthesized circuits are reduced. Experimental results have shown that, compared to the state-of-the-art methods, the TLG count is reduced by 8% and logic depth is reduced by 46%.

关键词： Logic gates field programmable gate arrays Delays Boolean functions Cost function Memristors Magnetoelectronics

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A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

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Quantifying the cost and benefit of latency insensitive communication on FPGAs 14

Quantifying the cost and benefit of latency insensitive comm...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (FPGA)

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A power side-channel-based digital to analog converter for xilinx FPGAs 14

A power side-channel-based digital to analog converter for x...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Hutchings, Brad L. Monson, Joshua Savory, Danny Keeley, Jared Department of Electrical and Computer Engineering Brigham Young University Provo UT United States

ISBN: (纸本)9781450326711

A novel Digital to Analog Converter (DAC) modulates the overall power consumption of an FPGA by disabling/enabling short circuits programmed into the interconnect. The power pin of the FPGA serves as the output of the DAC. The DAC achieves high linearity and can be used to implement applications in communications, security, etc. The shortcircuit-based DAC consumes 1/3 the area of an alternative shift-register-based DAC that is presented for the sake of comparison.

关键词： field programmable gate arrays (FPGA)

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A soft error vulnerability analysis framework for xilinx FPGAs 14

A soft error vulnerability analysis framework for xilinx FPG...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based FPGAs provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of FPGA designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (FPGA)

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Synchronous integrator based on digital control system for silicon micromachined gyroscope

Synchronous integrator based on digital control system for s...

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2015 IEEE international symposium on Inertial Sensors and Systems (ISISS) proceedings

作者： Cheng Yang Hongsheng Li School of Instrument Science and Engineering Southeast University Nanjing China

For the decoupled dual-mass silicon Micromachined gyroscope developed by Southeast University, drive mode and sense mode are analyzed. In order to improve the precision of silicon Micromachined gyroscope, the demodulation algorithm based on synchronous integrator circuit for gyroscope digital control system is proposed. Combining with Automatic Gain Control (AGC) and Phase-Locked Loop (PLL) technology, the closed-loop control of drive mode and high precision output of sense mode of silicon Micromachined gyroscope have been implemented. In order to verify the effect of the synchronous integrator circuit applied in gyroscope control system, the Print Circuit Board (PCB) based on field programmable gate-Array (FPGA) digital circuit is manufactured and the corresponding experiment is carried out. The results of test show that the synchronous integrator demodulation algorithm of digital control system for silicon Micromachined gyroscope has achieved good performance. The bias stability of tested gyroscope is 0.2 o /hr and the angle random walk is measured to be 0.14 o /√hr. The results demonstrate that the proposed synchronous integrator demodulation scheme is effective.

关键词： Gyroscopes Demodulation Silicon Switches Digital control field programmable gate arrays

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Acceleration of nested conditionals on CGRAs via trigger scheme 15

Acceleration of nested conditionals on CGRAs via trigger sch...

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IEEE international Conference on Computer-Aided Design

作者： Shouyi Yin Pengcheng Zhou Leibo Liu Shaojun Wei Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9781467383899

Coarse-Grained Reconfigurable Architecture (CGRA) is a promising accelerator when considering both high performance and high power-efficiency. One of the challenges that CGRAs are confronting is to accelerate loops with control flow (if-then-else structures). Existing techniques employ predication to accelerate the conditionals but cannot accelerate nested conditionals efficiently. The state-of-the-art method dual issue scheme issues instructions from both the branch paths and then executes only the instructions from the path chosen by a predicate. But it also cannot handle nested conditionals. In this paper, we propose a solution to map loops with nested conditionals on a CGRA for the Triggered Instruction Architecture (TIA) paradigm - in which lacks compiler support. Experimental results show:We can accelerate loop kernels with nested conditionals via trigger scheme average of 1.41×, 1.79× and 1.29× better performance compared to partial predication, full predication and dual issue scheme respectively.

关键词： Acceleration Registers Junctions Computer architecture Kernel field programmable gate arrays Power demand

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Dynamic voltage & frequency scaling with online slack measurement 14

Dynamic voltage & frequency scaling with online slack measur...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Levine, Joshua M. Stott, Edward Cheung, Peter Y. K. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450326711

Timing margins in FPGAs are already significant and as process scaling continues they will have to grow to guarantee operation under increased variation. Margins enforce worst-case operation even in typical conditions and result in devices operating more slowly and consuming more energy than necessary. This paper presents a method of dynamic voltage and frequency scaling that uses online slack measurement to determine timing headroom in a circuit while it is operating and scale the voltage and/or frequency in response. Doing so can significantly reduce power consumption or increase throughput with a minimal overhead. The method is demonstrated on a number of benchmark circuits under a range of operating conditions, constraints and optimisation targets.

关键词： field programmable gate arrays (FPGA)

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