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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Accelerating Machine Learning Kernel in Hadoop Using FPGAs

Accelerating Machine Learning Kernel in Hadoop Using FPGAs

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IEEE/acm international symposium on Cluster Computing and the Grid (CCGRID)

作者： Katayoun Neshatpour Maria Malik Houman Homayoun Department of Electrical and Computer Engineering George Mason University

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. % Considering the time dedicated to create such specialized architectures, a model that estimates the potential speedup achievable through offloading various parts of the algorithm to specialized hardware would be necessary. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Signboards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment.

关键词： Acceleration Kernel Computer architecture Hardware field programmable gate arrays Big data Machine learning algorithms

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Hardware acceleration of database operations 14

Hardware acceleration of database operations

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Casper, Jared Olukotun, Kunle Pervasive Parallelism Laboratory Stanford University United States

ISBN: (纸本)9781450326711

As the amount of memory in database systems grows, en-tire database tables, or even databases, are able to t in the system's memory, making in-memory database operations more prevalent. This shift from disk-based to in-memory database systems has contributed to a move from row-wise to columnar data storage. Furthermore, common database workloads have grown beyond online transaction process-ing (OLTP) to include online analytical processing and data mining. These workloads analyze huge datasets that are of-ten irregular and not indexed, making traditional database operations like joins much more expensive. In this paper we explore using dedicated hardware to ac-celerate in-memory database operations. We present hard-ware to accelerate the selection process of compacting a sin-gle column into a linear column of selected data, joining two sorted columns via merging, and sorting a column. Finally, we put these primitives together to accelerate an entire join operation. We implement a prototype of this system using FPGAs and show substantial improvements in both absolute throughput and utilization of memory bandwidth. Using the prototype as a guide, we explore how the hardware resources required by our design change with the desired throughput.

关键词： field programmable gate arrays (FPGA)

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Square-rich fixed point polynomial evaluation on FPGAs 14

Square-rich fixed point polynomial evaluation on FPGAs

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Xu, Simin Fahmy, Suhaib A. McLoughlin, Ian V. Xilinx Asia Pacific Singapore School of Computer Engineering Nanyang Technological University Singapore School of Information Science and Technology University of Science and Technology of China China

ISBN: (纸本)9781450326711

Polynomial evaluation is important across a wide range of application domains, so signicant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial com-putation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an effcient polynomial evaluation algorithm, which reforms the evaluation process to include an increased num-ber of squaring steps. By using a squarer design that is more effcient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.

关键词： field programmable gate arrays (FPGA)

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A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs 14

A scalable sparse matrix-vector multiplication kernel for en...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Dorrance, Richard Ren, Fengbo Marković, Dejan EE Department UCLA Los Angeles CA 90095 United States

ISBN: (纸本)9781450326711

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

关键词： field programmable gate arrays (FPGA)

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A FPGA prototype design emphasis on low power technique 14

A FPGA prototype design emphasis on low power technique

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Hanyang, Xu Jian, Wang Jinmei, Lai Fudan University No.825 Zhangheng Rd shanghai China

ISBN: (纸本)9781450326711

In this paper, we propose a fully-functional Nanometer FPGA prototype chip. Compared to traditional single supply voltage, single threshold voltage design, we explore low power nanometer FPGA design challenges with Multi-Vt, Static Voltage Scaling and sleep mode technique. Compared to Dynamic Voltage Scaling (DVS), we make a table of Voltage-Delay parameter pairs under different voltage conditions so that timing information can be calculated by a Static Timing Analysis (STA) tool. Thus a lowest supply power is chosen among all results which meet the timing requirements. This approach would simplify the hardware design since we don't need a complex workload detection circuit compared to DVS system. By separating supply voltages, we can directly shutdown power supply of the unused circuits. Compared to inserting sleep transistor in pull-up or pull-down networks, we can eliminate the speed penalty cased by the additional sleep transistor. We implement a tile-based heterogeneous architecture with island style routing and embedded specific blocks such as DSP and memory. The array size is 6431 (RowCol) including 6424 CLBs. The final design is fabricated using a 1P10M 65-nm bulk CMOS process. Test results show a 53% reduction in static power compared to a commercial FPGA device which is also fabricated in 65nm process and has a similar array size.

关键词： field programmable gate arrays (FPGA)

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MPack: Global memory optimization for stream applications in high-level synthesis 14

MPack: Global memory optimization for stream applications in...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Vasiljevic, Jasmina Chow, Paul Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781450326711

One of the challenges in designing high-performance FPGA applications is fine-tuning the use of limited on-chip memory storage among many buffers in an application. To achieve desired performance the designer faces the burden of packaging such buffers into on-chip memories and manually optimizing the utilization of each memory and the throughput of each buffer. In addition, the application memories may not match the word width or depth of the physical on-chip memories available on the FPGA. This process is time consuming and non-trivial, particularly with a large number of buffers of various depths and bit widths. We propose a tool, MPack, which globally optimizes on-chip memory use across all buffers for stream applications. The goal is to speed up development time by providing rapid design space exploration and relieving the designer of lengthy low-level iterations. We introduce new high-level pragmas allowing the user to specify global memory requirements, such as an application's on-chip memory budget and data throughput. We allow the user to quickly generate a large number of memory solutions and explore the trade-off between memory usage and achievable throughput. To demonstrate the effectiveness of our tool, we apply the new high-level pragmas to an image processing benchmark. MPack effectively explores the design space and is able to produce a large number of memory solutions ranging from 10 to 100% in throughput, and from 12 to 100% in on-chip memory usage.

关键词： field programmable gate arrays (FPGA)

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CAD and routing architecture for interposer-based multi-FPGA systems 14

CAD and routing architecture for interposer-based multi-FPGA...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Pereira, Andre Hahn Betz, Vaughn Computer and Digital Systems Engineering Department-Escola Politécnica University of São Paulo São Paulo SP Brazil Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

Interposer-based multi-FPGA systems are composed of mul-tiple FPGA dice connected through a silicon interposer. Such devices allow larger FPGA systems to be built than one monolithic die can accomodate and are now commercially available. An open question, however, is how efficient such systems are compared to a monolithic FPGA, as the num-ber of signals passing between dice is reduced and the signal delay between dice is increased in an interposer system vs. a monolithic FPGA. We create a new version of VPR to investigate the archi-tecture of such systems, and show that by modifying the placement cost function to minimize the number of signals that must cross between dice we can reduce routing demand by 18% and delay by 2%. We also show that the signal count between dice and the signal delay between dice are key archi-tecture parameters for interposer-based FPGA systems. We find that if an interposer supplies (between dice) 60% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is little impact on the routability of circuits. Smaller routing capacities in the interposer do im-pact routability however: minimum channel width increases by 20% and 50% when an interposer supplies only 40% and 30% of the within-die routing, respectively. The interposer also impacts delay, increasing circuit delay by 34% on aver-age for a 1 ns interposer signal delay and a four-die system. Reducing the interposer delay has a greater benefit in im-proving circuit speed than does reducing the number of dice in the system.

关键词： field programmable gate arrays (FPGA)

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Towards interconnect-adaptive packing for FPGAs 14

Towards interconnect-adaptive packing for FPGAs

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Luu, Jason Rose, Jonathan Anderson, Jason Dept. Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

In order to investigate new FPGA logic blocks, FPGA ar-chitects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to cre-ate such CAD tools can be a time-consuming process that can significantly limit the number and variety of architec-tures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from im-practically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being in-vestigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common inter-connect structures that are used to create many kinds of use-ful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing , pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modi-fications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultane-ously expanding the scope of architectures that can be ex-plored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower crit-ical path delay. We obtain a 6 to 7-fold speedup for archi-tectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

关键词： field programmable gate arrays (FPGA)

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A photoacoustics based continuous non-invasive blood glucose monitoring system

A photoacoustics based continuous non-invasive blood glucose...

引用

IEEE international Workshop on Medical Measurement and Applications (MEMEA)

作者： Praful P. Pai Pradyut K. Sanki Swapna Banerjee Department of Electronics & Electrical Communication Engineering Indian Institute of Technology Kharagpur Kharagpur India

The paper examines the use of photoacoustic spectroscopy (PAS) for making continuous non-invasive blood glucose measurements. An apparatus for performing photoacoustic (PA) measurements is constructed and the technique is verified in vitro and in vivo through measurements on glucose solutions and live tissue. The signal amplitude is observed to increase with the glucose concentration in both cases. A linear calibration method is applied on each individual to obtain a glucose concentration value from each PA measurement. The glucose values obtained are compared with reference glucose concentrations measured using a standard glucose meter, giving a mean absolute difference (MAD) of 23.75 mg/dl and a mean absolute relative difference (MARD) of 18.03%. A plot of 196 measurement pairs taken over 30 normal subjects on a Clarke Error Grid gives a point distribution of 67.86%, 31.12%, 0.0%, 1.02% and 0.0% over zones A to E of the grid. This performance is an improvement over those obtained previously using PAS and point to the potential of the technique for non-invasive glucose measurements. An FPGA based reconfigurable embedded architecture is proposed for high speed data acquisition, noise reduction and display of PA measurements. The architecture operates at 274.823 MHz on a Xilinx Virtex-II Pro FPGA providing an SNR improvement of 30 dB and enabling a portable blood glucose monitoring system.

关键词： Sugar Blood Biomedical measurement field programmable gate arrays Computer architecture Biomedical optical imaging Wavelength measurement

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A study of manycore shared Memory Architecture as a way to build SOC applications 15

A study of manycore shared Memory Architecture as a way to b...

引用

Simulation Multiconference

作者： Yosi Ben Asher Yousef Shajrawi Y. Gendel Gadi Haber Oren Segal CS. Dept. University of Haifa IBM Intel EE dep. UMass Lowell

ISBN: (纸本)9781510801011

Manycore shared memory architectures hold a significant premise to speed up and simplify SOCs. Using many homogeneous small-cores will allow replacing the hardware accelerators of SOCs by parallel algorithms communicating through shared memory. Currently shared memory is realized by maintaining cache-consistency across the cores, caching all the connected cores to one main memory module. This approach, though used today, is not likely to be scalable enough to support the high number of cores needed for highly parallel SOCs. Therefore we consider a theoretical scheme for shared memory wherein: the shared address space is divided between a set of memory modules; and a communication network allows each core to access every such module in parallel. Load-balancing between the memory modules is obtained by rehashing the memory address-space. We consider practical aspects involved with a practical realization of this scheme, e.g., how will the wire complexity of the communication network affect the execution time. We have designed a simple generic shared memory architecture, synthesized it to 2,4,8,16,..., 1024 - cores for FPGA virtex-7 and evaluated it on several parallel programs. The synthesis results and the execution measurements show that, for the FPGA, all problematic aspects of this construction can be resolved. For example, unlike ASICs, the growing complexity of the communication network is absorbed by the FPGA's routing grid and by its routing mechanism. This makes this type of architectures particularly suitable for FPGAs. We used 32-bits modified PACOBLAZE cores and tested different parameters of this architecture verifying its ability to achieve high speedups. The results suggest that re-hashing is not essential and one hash-function suffice (compared to the family of universal hash functions that is needed by the theoretical construction).

关键词： networks(communications) accessor core SYNTHETIC ORGANIC CHEMICALS shared memory Memory architecture shared memory systems field programmable gate arrays Core samples execution time hardware accelerator address space

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