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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Sensing nanosecond-scale voltage attacks and natural transients in FPGAs 13

Sensing nanosecond-scale voltage attacks and natural transie...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Zick, Kenneth M. Srivastav, Meeta Zhang, Wei French, Matthew Arlington VA United States Virginia Tech. Blacksburg VA United States University of Virginia Charlottesville VA United States

ISBN: (纸本)9781450318877

Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented;its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Accelerating ncRNA homology search with FPGAs 13

Accelerating ncRNA homology search with FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： McVicar, Nathaniel Ruzzo, Walter L. Hauck, Scott Department of Electrical Engineering University of Washington Seattle WA 98195 United States Department of Computer Science and Engineering Department of Genome Sciences Fred Hutchinson Cancer Research Center Seattle WA 98109 United States

ISBN: (纸本)9781450318877

Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in the linear RNA molecule. Because of these characteristics, algorithms that search for ncRNAs belonging to known families are computationally expensive, often taking many CPU weeks to run. To improve the speed of this search, multiple search algorithms arranged into a series of progressively more stringent filters can be used. In this paper, we present an FPGA based implementation of some of these algorithms. This is the first FPGA based approach to attempt to accelerate multiple filters used in ncRNA search. The FPGA is reconfigured for each filter, resulting in a total system speedup of 25x when compared with a single CPU. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Power estimation tool for system on programmable chip based platforms (abstract only) 14

Power estimation tool for system on programmable chip based ...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Santhosh Kumar Rethinagiri Oscar Palomar Adrian Cristal Osman Unsal BSC - Microsoft Research Center Barcelona Spain BSC - Mircrosoft Research Center Barcelona Spain

ISBN: (纸本)9781450326711

The ever increasing complexity of the applications result in the development of power hungry processors. There is a scarcity of standalone tools that have a good trade off between estimation speed and accuracy to estimate power/energy at an earlier phase of design flow. There are very few tools that addresses the design space exploration issue based on power and energy. In this paper, we propose a virtual platform based standalone power and energy estimation tool for System-on-programmable Chip (SoPC) embedded platforms, which is independent of in-house tools. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for the different parts of the system. This is a onetime activity. In the second step, a simulation based virtual platform framework is developed to evaluate accurately the activities used in the related power models developed in the first step. The combination of the two steps lead to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed tool is also scalable for exploring complex embedded multi-core *** effectiveness of our proposed tool is validated through dualcore RISC processor designed around the FPGA board and extended to accommodate futuristic multi-core processors for a reliable energy based design space exploration. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks such as Multimedia, EEMBC and SPEC2006. Estimated power values are compared to real board measurements and also to McPAT. Our obtained power/energy estimation results provide less than 9% of error for heterogeneous MPSoC based system and are 200% faster compared to other

关键词： power/energy estimation fpga systemc heterogeneous architecture asic tlm speedup multicore functional power models design space exploration virtual platform accuracy

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Heracles: A tool for fast RTL-based design space exploration of multicore processors 13

Heracles: A tool for fast RTL-based design space exploration...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Kinsy, Michel A. Pellauer, Michael Devadas, Srinivas Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA United States Intel Corporation VSSAD Group Hudson MA United States

ISBN: (纸本)9781450318877

This paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of different topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly configure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://***/heracles. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Placement of repair circuits for in-field FPGA repair 13

Placement of repair circuits for in-field FPGA repair

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Wirthlin, Michael Jensen, Josh Wilson, Alex Howes, Will Wen, Shi-Jie Wong, Rick Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84606 United States Cisco Systems San Jose CA 95134 United States

ISBN: (纸本)9781450318877

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This paper presents a method for repairing FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the FPGA. This approach relies on logic placement to create "repair" circuits that avoid specific logic blocks. Three repair placement algorithms will be presented that generate a complete set of repair designs during the conventional placement process. The number of repairs needed to create a complete repair set depends heavily on the utilization of the FPGA resources. The three algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. The best repair placement approach described in the paper generates a full set of repair circuits at a computation cost of 16X that of a conventional placer and with circuits of comparable quality. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Area-efficient near-associative memories on FPGAs 13

Area-efficient near-associative memories on FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Dhawan, Udit DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Associative memories can map sparsely used keys to values with low latency but can incur heavy area overheads. The lack of customized hardware for associative memories in today's mainstream FPGAs exacerbates the overhead cost of building these memories using the fixed address match BRAMs. In this paper, we develop a new, FPGA-friendly, memory architecture based on a multiple hash scheme that is able to achieve near-associative performance (less than 5% of evictions due to conflicts) without the area overheads of a fully associative memory on FPGAs. Using the proposed architecture as a 64KB L1 data cache, we show that it is able to achieve near-associative miss-rates while consuming 6-7× less FPGA memory resources for a set of benchmark programs from the SPEC2006 suite than fully associative memories generated by the Xilinx Coregen tool. Benefits increase with match width, allowing area reduction up to 100×. At the same time, the new architecture has lower latency than the fully associative memory - 3.7 ns for a 1024-entry flat version or 6.1 ns for an area-efficient version compared to 8.8 ns for a fully associative memory for a 64b key. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Fully-functional FPGA prototype with fine-grain programmable body biasing 13

Fully-functional FPGA prototype with fine-grain programmable...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Hioki, Masakazu Sekigawa, Toshihiro Nakagawa, Tadashi Koike, Hanpei Matsumoto, Yohei Kawanami, Takashi Tsutsumi, Toshiyuki Tsukuba Japan Tokyo University of Marine Science and Technology Tokyo Japan Kanazawa Institute of Technology Kanazawa Japan Meiji University Kawasaki Japan

ISBN: (纸本)9781450318877

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Video-rate stereo matching using Markov random field TRW-S inference on a hybrid CPU+FPGA computing platform 13

Video-rate stereo matching using Markov random field TRW-S i...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Choi, Jungwook Rutenbar, Rob A. Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign 201 N. Goodwin Avenue Urbana IL 61801-2302 United States Department of Computer Science University of Illinois at Urbana-Champaign 201 N. Goodwin Avenue Urbana IL 61801-2302 United States

ISBN: (纸本)9781450318877

We demonstrate a video-rate stereo matching system implemented on a hybrid CPU+FPGA platform (Convey HC-1). Emerging applications such as 3D gesture recognition and automotive navigation demand fast and high quality stereo vision. We describe a custom hardware-accelerated Markov Random field inference system for this task. Starting from a core architecture for streaming tree-reweighted message passing (TRW-S) inference, we describe the end-to-end system engineering needed to move from this single frame message update to full stereo video. We partition the stereo matching procedure across the CPU and the FPGAs, and apply both function-level pipelining and frame-level parallelism to achieve the required speed. Experimental results show that our system achieves a speed of 12 frames per second for challenging video stereo matching tasks. We note that this appears to be the first implementation of TRW-S inference at video rates, and that our system is also significantly faster than several recent GPU implementations of similar stereo inference methods based on belief propagation (BP). © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Word-length optimization beyond straight line code 13

Word-length optimization beyond straight line code

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Boland, David P. Constantinides, George A. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450318877

The silicon area benefits that result from word-length optimization have been widely reported by the FPGA community. However, to date, most approaches are restricted to straight line code, or code that can be converted into straight line code using techniques such as loop-unrolling. In this paper, we take the first steps towards creating analytical techniques to optimize the precision used throughout custom FPGA accelerators for algorithms that contain loops with data dependent exit conditions. To achieve this, we build on ideas emanating from the software verification community to prove program termination. Our idea is to apply word-length optimization techniques to find the minimum precision required to guarantee that a loop with data dependent exit conditions will terminate. Without techniques to analyze algorithms containing these types of loops, a hardware designer may elect to implement every arithmetic operator throughout a custom FPGA-based accelerator using IEEE-754 standard single or double precision arithmetic. With this approach, the FPGA accelerator would have comparable accuracy to a software implementation. However, we show that using our new technique to create custom fixed and floating point designs, we can obtain silicon area savings of up to 50% over IEEE standard single precision arithmetic, or 80% over IEEE standard double precision arithmetic, at the same time as providing guarantees that the created hardware designs will work in practice. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Accelerating subsequence similarity search based on dynamic time warping distance with FPGA 13

Accelerating subsequence similarity search based on dynamic ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Wang, Zilong Huang, Sitao Wang, Lanjun Li, Hao Wang, Yu Yang, Huazhong E.E. Dept. TNLIST Tsinghua University Beijing China IBM Research China Beijing China

ISBN: (纸本)9781450318877

Subsequence search, especially subsequence similarity search, is one of the most important subroutines in time series data mining algorithms, and there is increasing evidence that Dynamic Time Warping (DTW) is the best distance metric. However, in spite of the great effort in software speedup techniques, including early abandoning strategies, lower bound, indexing, computation-reuse, DTW still cost too much time for many applications, e.g. 80% of the total time. Since DTW is a 2-Dimension sequential dynamic search with quite high data dependency, it is hard to use parallel hardware to accelerate it. In this work, we propose a novel framework for FPGA based subsequence similarity search and a novel PE-ring structure for DTW calculation. This framework utilizes the data reusability of continuous DTW calculations to reduce the bandwidth and exploit the coarse-grain parallelism;meanwhile guarantees the accuracy with a two-phase precision reduction. The PE-ring supports on-line updating patterns of arbitrary lengths, and utilizes the hard-wired synchronization of FPGA to realize the fine-grained parallelism. It also achieves flexible parallelism degree to do performance-cost trade-off. The experimental results show that we can achieve several orders of magnitude speedup in accelerating subsequence similarity search compared with the best software and current GPU/FPGA implementations in different datasets. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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