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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Heterogeneous 3-D stacking, can we have the best of both (Technology) worlds? 13

Heterogeneous 3-D stacking, can we have the best of both (Te...

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2013 acm international symposium on Physical Design, ISPD 2013

作者： Madden, Liam Xilinx Inc. 2100 Logic Drive San Jose CA 95124 United States

ISBN: (纸本)9781450318679

Since the advent of integrated circuit technology in 1958, the industry has focused primarily on monolithic integration. Unfortunately, due to physical and economic issues, the vast majority of high performance analog chips, high density memory chips, and high performance digital chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). The heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware 13

A hardware-oriented dynamically adaptive disparity estimatio...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Akin, Abdulkadir Baz, Ipek Atakan, Baris Boybat, Irem Schmid, Alexandre Leblebici, Yusuf STI EPFL 1015 Lausanne Switzerland EEE METU Ankara Turkey EE SU Istanbul Turkey

ISBN: (纸本)9781450319027

The computational complexity of disparity estimation algorithms and the need of large size and bandwidth for the external and internal memory make the real-time processing of disparity estimation challenging, especially for High Resolution (HR) images. This paper proposes a hardware-oriented adaptive window size disparity estimation (AWDE) algorithm and its real-time reconfigurable hardware implementation that targets HR video with high quality disparity results. The proposed algorithm is a hybrid solution involving the Sum of Absolute Differences and the Census cost computation methods to vote and select the best suitable disparity candidates. It utilizes a pixel intensity based refinement step to remove faulty disparity computations. The AWDE algorithm dynamically adapts the window size considering the local texture of the image to increase the disparity estimation quality. The proposed reconfigurable hardware of the AWDE algorithm enables handling 60 frames per second on Virtex-5 FPGA at a 1024x768 XGA video resolution for a 120 pixel disparity range. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only) 13

Hardware acceleration of TEA and XTEA algorithms on FPGA, GP...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vivek Venugopal Devu Manikantan Shila United Technologies Research Center E Hartford CT USA

ISBN: (纸本)9781450318877

field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

关键词： cryptography graphics processing units tiny encryption algorithm field programmable gate arrays parallel processing

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Indirect connection aware attraction for FPGA clustering (abstract only) 13

Indirect connection aware attraction for FPGA clustering (ab...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Meng Yang Jiarong Tong A.E.A. Almaini State Key Lab of ASIC Fudan University Shanghai China Edinburgh Napier University Edinburgh United Kingdom

ISBN: (纸本)9781450318877

Indirect connection aware attraction clustering algorithm is proposed for clustered field programmable gate array architecture model to achieve simultaneously optimization of several performance metrics. A new cost function considers the attraction of the subsequent basic logic elements (BLEs) to the selected cluster, the number of the used pins already in the cluster, as well as critical path delay. The attractions of which BLEs are directly and indirectly connected to the selected cluster are taken into account. As a result, more external nets are absorbed into clusters, less number of pins per cluster and fewer clusters are required. Hence, smaller channel width is required for routing and speed of the design is improved. Performance comparisons are carried out in details with respect to state-of-the-art clustering techniques interconnect resource aware clustering (iRAC) and many-objective clustering (MO-Pack). Results show that the proposed algorithm outperforms these two clustering approaches with achievements of 38.8% and 42.2% respectively in terms of channel widths and 40.1% and 44.8% respectively in terms of number of external nets but with no critical path and area overhead.

关键词： FPGAs computer aided design clustering optimization field-programmable gate arrays

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FPGA-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only) 13

Hybrid masking using intra-masking dual-rail memory on LUT f...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Anh-Tuan Hoang Takeshi Fujino Ritsumeikan University Shiga prefecture Kusatsu city Japan

ISBN: (纸本)9781450318877

In current countermeasure design trends against Different Power Analysis (DPA), security at gate level is required in addition to the security algorithm. Several Dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate Array (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel Hybrid Masking implementations using Intra-Masking Dual-rail Memory (IMDRM) approach for Side-channel-resistant AES. The hybrid masking scheme includes an additive mask and a multiplicative mask. The additive masking scheme utilizes a dual-rail memory, in which all unsafe nodes, such as unmasking and masking, the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The multiplicative masking scheme is then applied over the additive masked values. It removes the joint-leakage, which is caused by the joint processing of the masks and the masked values inside the dual-rail memory. The design is independent of the cryptographic algorithm and persistent with SCA attacks even after 1,000,000 traces. It also occupied smaller hardware size than most other advanced SCA resistant implementations such as the Wave Dynamic Differential Logic, the Masked Dual-Rail Pre-charge Logic, and the Intra-Masking Dual-Rail Memory.

关键词： SCA resistance differential power analysis (DPA) side-channel attack masking intra-masking dual-rail memory on LUT dual-rail memory field programmable gate array (FPGA) hybrid masking AES

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Defect recovery in nanodevice-based programmable interconnects (abstract only) 13

Defect recovery in nanodevice-based programmable interconnec...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Bingjun Xiao UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

This work focuses on defect tolerance for nanodevice-based programmable interconnects of FPGAs. A single nanodevice can function as a routing switch in place of a pass transistor and its six-transistor SRAM cell in conventional FPGAs. Defects of nanodevices in programmable interconnects are manifested as losses of configurability and can be categorized into stuck- open defect and stuck- closed defect. First, we show that the stuck-closed defects of nanodevices have a much higher impact than the stuck-open defects. Instead of simply avoiding the stuck-closed defects, we recover them by treating them as shorting constraints in the routing. We develop a scalable algorithm to perform timing-driven routing under these extra constraints. We extend the idea of the resource negotiation to balance the goals of timing and routability under shorting constraints. We also develop several techniques to guide the router to map the shorting clusters to those nets with more shared paths for better utilization of routing resources while automatically balancing it with circuit performance. We also enhance the placement algorithm to recover logic blocks which become virtually unusable due to shorted pins. Simulation results show that at the up-to-date level of nanodevice defects (108-1011x higher than CMOS), compared to the simple avoidance method, our approach reduces the degradation of resource usage by 87%, improves the routability by 37%, and reduce the degradation of circuit performance by 36%, at a negligible overhead of tool runtime.

关键词： nanodevice defect tolerance route programmable interconnects placement

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A Fast Discrete Placement Algorithm for FPGAs 12

A Fast Discrete Placement Algorithm for FPGAs

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (FPGA) placement simulated annealing

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Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

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