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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是321-330 订阅

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Voter insertion algorithms for FPGA designs using triple modular redundancy 10

Voter insertion algorithms for FPGA designs using triple mod...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

作者： Johnson, Jonathan M. Wirthlin, Michael J. Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84606 United States

ISBN: (纸本)9781605589114

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast four algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be reported. This paper will demonstrate that one of the algorithms provides the best overall timing performance results with an average 9.8% increase in critical path length over a triplicated design without voters. Another algorithm provides far better area results at a slightly higher timing cost (an average 2.1% area increase over a triplicated design without voters). Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Bit-level optimization for high-level synthesis and FPGA-based acceleration 10

Bit-level optimization for high-level synthesis and FPGA-bas...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

作者： Zhang, Jiyu Zhang, Zhiru Zhou, Sheng Tan, Mingxing Liu, Xianhua Cheng, Xu Cong, Jason MicroProcessor Research and Development Center Peking University Beijing China Computer Science Department University of California Los Angeles CA 90095 United States PKU/UCLA Joint Research Institute in Science and Engineering China AutoESL Design Technologies Los Angeles CA 90064 United States

ISBN: (纸本)9781605589114

Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Haptic Rendering of Deformable Objects Using a Multiple FPGA Parallel Computing Architecture 10

Haptic Rendering of Deformable Objects Using a Multiple FPGA...

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18th acm international symposium on field-programmable gate arrays

作者： Mandavikhah, Behzad Mafi, Ramin Sirouspour, Shahin Nicolici, Nicola McMaster Univ Hamilton ON Canada

ISBN: (纸本)9781605589114

High-fidelity simulations of haptic interaction with deformable objects is computationally challenging. In this paper, hardware-based parallel computing is proposed for finite-element (FE) analysis of soft-object deformation models. A distributed implementation of the Preconditioned Conjugate Gradient (PCG) algorithms on N field programmable gate Array (FPGA) devices can solve the large system of equations arising from FE models at high update rates required for stable haptic interaction. Massive parallelization of the computations is achieved by customizing the hardware architecture to the problem at hand and concurrently employing a large number of adaptive fixed-point computing units. An implementation of this scalable hardware accelerator on four Altera EP3SE110 FPGA devices is capable of performing 230.4 Giga Operations per second in Sparse Matrix by Vector (SpMxV) multiplication. This architecture has successfully enabled real-time simulation of haptic interaction with a 3-dimensional FE model of 6000 nodes at an update rate of 200 Hz. Both static and dynamic linear elastic models have been successfully simulated.

关键词： field-programmable gate array (FPGA) Finite-element method (FEM) Conjugate Gradient (CG) Soft-object deformation

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Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

Regular fabric design with ambipolar CNTFETs for FPGA and st...

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2010 IEEE/acm international symposium on Nanoscale Architectures, NANOARCH 2010

作者： De Marchi, Michele Ben Jamaa, M. Haykel De Micheli, Giovanni EPFL Lausanne Switzerland CEA-LETI-MINATEC 17 Rue des Martyrs F-38054 Grenoble France

ISBN: (纸本)9781424480180

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs [1]. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18x with respect to 4-input LUTs in terms of areaxnormalized delay. ©2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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The Impact of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs) 10

The Impact of Interconnect Architecture on Via-Programmed St...

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18th acm international symposium on field-programmable gate arrays

作者： Ahmed, Usman Lemieux, Guy G. F. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781605589114

In this paper, we evaluate the performance of an FPGA-like interconnect fabric for structured ASICs which is based upon fixed metal and programmable vias. We call this type of device a via-programmed structured ASIC or VPSA. We look at two different types of VPSA routing fabrics: one uses jumper wiring and the other uses crossover wiring. The performance of these fabrics is compared against an ASIC-like interconnect fabric, otherwise known as a metal-programmed structured ASIC or MPSA, which can be configured by customizing metal and via layers. We study the impact of these routing fabrics on cost, area, power and delay metrics. The results for different fabrics span a wide range, suggesting the routing architecture plays a very important role in their overall performance and it should be thoroughly researched.

关键词： Structured ASICs Via programmable Fabric

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FPGA Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th acm international symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the FPGA interconnect by 14%.

关键词： field-programmable gate arrays FPGAs power optimization low-power design logic synthesis technology mapping

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A 3D-Audio Reconfigurable Processor 10

A 3D-Audio Reconfigurable Processor

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18th acm international symposium on field-programmable gate arrays

作者： Theodoropoulos, Dimitris Kuzmanov, Georgi Gaydadjiev, Georgi Delft Univ Technol Dept Elect Engn Comp Engn Lab NL-2600 GA Delft Netherlands

ISBN: (纸本)9781605589114

Various multimedia communication systems based on 3D-Audio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators exploiting the beamforming and the Wave field Synthesis algorithms. The theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working FPGA prototype is compared against a software implementation on a Core2 Duo system. Results suggest that the proposed reconfigurable hardware solution can process data up to 2.4x faster than the software approach, while power consumption is approximately 7 Watts according to the Xilinx XPower report.

关键词： 3D-Audio Wave field Synthesis Beamforming Reconfigurable Computing Communication Systems

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3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory 10

3D-NonFAR: Three-dimensional non-volatile FPGA architecture ...

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proceedings of the 16th acm/IEEE international symposium on Low power electronics and design

作者： Chen, Yibo Zhao, Jishen Xie, Yuan Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)9781450301466

Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero boot-up delay, real-time reconfigurability, and superior energy efficiency. This paper presents a novel threedimensional (3D) non-volatile FPGA architecture (3D-Non- FAR) using phase change memory (PCM) and 3D die stacking techniques. Basic structures in a conventional FPGA architecture are renovated with PCM, and components are repartitioned and reorganized in 3D-NonFAR to allow an efficient 3D integration of PCM elements. 3D-NonFAR not only preserves the advantages of existing non-volatile FPGAs, but also provides high integration density, high performance, and bit-level programmability, which enable PCM as a universal memory replacement in FPGAs. Evaluation results show that 3D-NonFAR has smaller footprint, higher performance, and lower power consumption compared with other FPGA counterparts. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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FPGA 2008 - Sixteenth acm/sigda international symposium on field-programmable gate arrays

FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on F...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

ISBN: (纸本)9781595939340

The proceedings contain 24 papers. The topics discussed include: designing with extreme parallelism;high-quality, deterministic parallel placement for FPGAs on commodity hardware;enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals;mapping for better than worst-case delays in LUT-based FPGA designs;a complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs;efficient ASIP design for configurable processors with fine-grained resource sharing;pattern-based behavior synthesis for FPGA resource reduction;modeling routing demand for early-stage FPGA architecture development;and trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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