Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programm...
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ISBN:
(纸本)9781605589114
Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmablegate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.
Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmablegatearrays. These architectures are...
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ISBN:
(纸本)9781605589114
Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmablegatearrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.
This work explores architectural ideas to build a scalable programmable quantum gate array (PQGA) by exploiting unique quantum effects such as superposition and entanglement/teleportation. In contrast to prior studies...
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ISBN:
(纸本)9781605589114
This work explores architectural ideas to build a scalable programmable quantum gate array (PQGA) by exploiting unique quantum effects such as superposition and entanglement/teleportation. In contrast to prior studies, in which a quantum computing machine is implemented either as an ASIC-like special-purpose chip tailored for specific algorithm or as a general-purpose processor based on the Von-Neumann model, we propose a PQGA architecture that is reconfigurable for different domain-specific applications with high logic density. The PQGA architecture is novel in several aspects, among which its interconnect work is built with "virtual wires" implemented with quantum entanglement. In this work, we propose various designs for logic block, interconnect network, and design strategies to construct large designs in PQGA. Our goal is to investigate new architectural ideas based on reconfigurable computing method in order to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum comput- ing. Leveraging the extensive groundwork in quantum computing and algorithm design, we provide estimation results to show that our proposed PQGA architecture can achieve not only high performance but also scalability. Finally, we benchmark our proposed PQGA architecture against previous quantum computer architecture and illustrate on average a 3x improvement in terms of logic density for the well-known Shor's quantum factoring algorithm.
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavo...
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ISBN:
(纸本)9781605584102
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web. Copyright 2009 acm.
This article presents the performance evaluation of two new diagonal routing tracks in FPGAs. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and rout...
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ISBN:
(纸本)9781605584102
This article presents the performance evaluation of two new diagonal routing tracks in FPGAs. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and routing to suit these architectures better. We conduct a series of experiments on these architecture with MCNC Benchmarks, where key parameters are varied over practical ranges and we conclude that the results are well in accordance, as predicted by the theory. Copyright 2009 acm.
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this archi...
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ISBN:
(纸本)9781605584102
In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems. Copyright 2009 acm.
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. Fo...
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ISBN:
(纸本)9781605584102
This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented. Copyright 2009 acm.
Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an ...
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ISBN:
(纸本)9781605584102
Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables- specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial FPGA architecture. Copyright 2009 acm.
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limite...
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ISBN:
(纸本)9781605584102
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limited regular expression support for wildcard patterns used by rules that represent polymorphic viruses. To reduce the amount of state needed to track so many regular expressions, PERG-Rx employs a lossy scheme which increases the rate of false positives detected as the required state grows. The scalability and dynamic updatability of the PERG-Rx architecture to database updates are also evaluated. Copyright 2009 acm.
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