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SmartOpt: An industrial strength framework logic synthesis

SmartOpt: An industrial strength framework logic synthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jang, Stephen Wu, Dennis Jarvin, Mark Chan, Billy Chung, Kevin Mishchenko, Alan Brayton, Robert Xilinx Inc United States University of California Berkeley United States

ISBN: (纸本)9781605584102

In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. This paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. This work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL. Xilinx Synthesis Technology (XST) reference flow was compared experimentally against the same flow augmented by SmartOpt. When applied to a set of 20 large industrial Virtex-5 benchmarks ranging from 17K to 69K 6- LUTs, the augmented flow produced 8.3% fewer LUTs and led to 2.1% higher operating frequency while keeping runtimes reasonable. With dual-LUT-merging, the LUT count is reduced by 22.7%, while increasing the operating frequency only by 0.7%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Towards automated ECOs in FPGAs

Towards automated ECOs in FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Andrew Brown, Stephen Zhu, Jianwen Safarpour, Sean Electrical and ComputerEngineering University of Toronto Canada Toronto Technology Center Altera Corporation Canada

ISBN: (纸本)9781605584102

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design;thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Choose-your-own-adventure routing: Lightweight load-time defect avoidance

Choose-your-own-adventure routing: Lightweight load-time def...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Rubin, Raphael DeHon, André Computer and Information Science University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd Street Philadelphia PA 19104 United States

ISBN: (纸本)9781605584102

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable hannel width, routes can tolerate 0.01% switch defect rates, raising yield from essentially 0% to near 100%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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A high-performance FPGA architecture for restricted machines

A high-performance FPGA architecture for restricted machines

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ly, Daniel L. Chow, Paul Department of Electrical and Computer Engineering University of Toronto Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605584102

ef>Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of is due to the fact that neural networks are usually as software running on general-purpose processors. to implement a neural network in software typically O(n2) problems - as a result, neural networks unable to provide the performance and scalability required non-academic settings. this paper, we investigate how FPGAs can be used take advantage of the inherent parallelism in neural networks provide a better implementation in terms of scalability performance. We will focus on the Restricted machine, a popular type of neural network, because architecture is particularly well-suited to hardware . The proposed, multi-purpose hardware framework designed to reduce the O(n2) problem into an O(n) implementation only requiring O(n) resources. The framework tested on a Xilinx Virtex II-Pro XC2VP70 FPGA at 100MHz. The resources support a Restricted machine of 128 x 128 nodes, which results in computational speed of 1.02 billion connection-updatesper- and a speed-up of 35 fold over an optimized C program running on a 2.8GHz Intel processor. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Scalable don't-care-based logic optimization and resynthesis

Scalable don't-care-based logic optimization and resynthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Mishchenko, Alan Brayton, Robert Jiang, Jie-Hong Roland Jang, Stephen Department of EECS University of California Berkeley United States Department of EE National Taiwan University Taiwan Xilinx Inc. San Jose CA United States

ISBN: (纸本)9781605584102

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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High-performance, energy-efficient platforms in-socket FPGA accelerators

High-performance, energy-efficient platforms in-socket FPGA ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Liu Oliver, Neal Bhushan, Chitlur Qigang, Wang Chen, Alvin Wenbo, Shen Zhihong, Yu Sheiman, Arthur McCallum, Ian Grecco, Joseph Mitchel, Henry Dong, Liu Gupta, Prabhat Intel Corporation

ISBN: (纸本)9781605584102

Growing demand for energy-efficient, high-performance systems has resulted in the growth of innovative heterogeneous computing system architectures that use FPGAs. FPGA-based architectures enable designers to implement custom instruction streams executing on potentially thousands of compute elements. Traditionally, FPGAs have been used as compute elements on PCI devices;however, this does not allow the FPGAs to be coprocessors. This paper describes a high-performance system architecture that is based on the Intel Xeon platform in which one or more FPGAs, acting as application accelerators, replace one or more processors in a dual/multi-processor (DP/MP) platform. The FPGA is thus connected directly to the Front Side Bus (FSB) and enjoys the same privileges as a processor, i.e., full participation in the coherency protocol, unrestricted access to system memory and to other processors via the high bandwidth, and low latency connection to the FSB. In addition, we also describe a software layer called the "Accelerator Abstraction Layer (AAL)", which provides a uniform, hardware- and/or platform-independent application interface. Applications written on AAL can be ported to multiple platforms that have different types of accelerators and the application does not have to be modified. In addition, the AAL also enables the developer/user to reprogram the FPGA on the fly (analogous to an operating system context switch) thereby utilizing the programmable nature of the FPGA. The resulting hardware/software stack creates a flexible and powerful platform for accelerator innovation and deployment. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Large-scale wire-speed packet classification on FPGAs

Large-scale wire-speed packet classification on FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jiang, Weirong Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)9781605584102

Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Although a plethora of research has been done in this area, wire-speed packet classification while supporting large rule sets remains difficult. This paper exploits the features provided by current FPGAs and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification. To fit the current largest rule set in the on-chip memory of the FPGA device, we propose several optimization techniques for the stateof- the-art decision-tree-based algorithm, so that the memory requirement is almost linear with the number of rules. Specialized logic is developed to support varying number of branches at each decision tree node. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization. Since our architecture is linear and memory based, on-the-fly update without disturbing the ongoing operations is feasible. The implementation results show that our architecture can store 10K real-life rules in on-chip memory of a single Xilinx Virtex-5 FPGA, and sustain 80 Gbps (i.e. 2 OC-768 rate) throughput for minimum size (40 bytes) packets. To the best of our knowledge, this work is the first FPGA-based packet classification engine that achieves wire-speed throughput while supporting 10K unique rules. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

VPR 5.0: FPGA CAD and architecture exploration tools with si...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Luu, Jason Kuon, Ian Jamieson, Peter Campbell, Ted Ye, Andy Fang, Wei Mark Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

The VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. This paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing architectures [29, 4, 16]. Single-driver routing has significantly different architectural and electrical properties from the multi-driver approach previously modelled, and is now employed in the majority of FPGAs sold. Second, the new release can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in FPGAs. Third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Intel atom processor core made FPGA-synthesizable

Intel atom processor core made FPGA-synthesizable

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Wang, Perry H. Collins, Jamison D. Weaver, Chris T. Kuttanna, Belliappa Salamian, Shahram Chinya, Gautham N. Schuchman, Ethan Schilling, Oliver Doil, Thorsten Steibl, Sebastian Wang, Hong Microarchitecture Research Lab Corporate Technology Group Intel Corporation Atom Processor Architecture Mobility Group Intel Corporation Germany Microprocessor Lab Corporate Technology Group Intel Corporation Germany

ISBN: (纸本)9781605584102

We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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