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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Power-aware RAM mapping for FPGA embedded memory blocks 06

Power-aware RAM mapping for FPGA embedded memory blocks

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Tessier, Russell Betz, Vaughn Neto, David Gopalsamy, Thiagaraja Department of Electrical and Computer Engineering University of Massachusetts Amherst MA United States Altera Toronto Technology Centre 151 Bloor St Toronto Ont. Canada Altera Corporation 101 Innovation Drive San Jose CA United States

ISBN: (纸本)1595932925

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance. Copyright 2006 acm.

关键词： field programmable gate arrays

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Design of a Single Event Upset (SEU) mitigation technique for programmable devices 06

Design of a Single Event Upset (SEU) mitigation technique fo...

引用

7th international symposium on Quality Electronic Design

作者： Baloch, S. Arslan, T. Stoica, A. Alba Centre Inst Syst Level Integrat Alba Campus Livingston EH54 7EG Scotland Univ Edinburgh Sch Elect & Engg Edinburgh EH8 9YL Midlothian Scotland NASA Jet Propuls Lab Pasadena CA 91109 USA

ISBN: (纸本)0769525237

This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.

关键词： Single event upset field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation programmable logic arrays Latches

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Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs 06

Analysis and experimental results of an FPGA-based strategy ...

引用

7th international symposium on Quality Electronic Design

作者： De Venuto, Daniela Reyneri, Leonardo Politecn Bari Bari Italy Politecn Torino Turin Italy

ISBN: (纸本)0769525237

This work describes an intensive investigation on the test strategy known as polynomial fitting that uses FPGA generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. The proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.

关键词： Production Circuit testing Automatic testing Polynomials Built-in self-test Signal generators Linearity Histograms Performance evaluation field programmable gate arrays

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Probabilistic delay budgeting for soft realtime applications 06

Probabilistic delay budgeting for soft realtime applications

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7th international symposium on Quality Electronic Design

作者： Ghiasi, Soheil Huan, Po-Kuan Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769525237

Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. This paradigm shaft calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multimedia applications on FPGAs show about 20% and 19% average energy and area improvement, respectively.

关键词： Timing Delay effects Hardware Flow graphs Application software Algorithm design and analysis Data flow computing Design methodology Stochastic processes field programmable gate arrays

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Dual-Vt design of FPGAs for subthreshold leakage tolerance 06

Dual-Vt design of FPGAs for subthreshold leakage tolerance

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7th international symposium on Quality Electronic Design

作者： Kumar, Akhilesh Anis, Mohab Univ Waterloo Dept ECE 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769525237

In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures.

关键词： field programmable gate arrays Subthreshold current Routing Switches Design automation Circuits Threshold voltage Logic design Sleep MOS devices

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. This architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. Through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). These switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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2004 acm/sigda twelfth international symposium on field programmable gate arrays

2004 ACM/SIGDA twelfth international symposium on field prog...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Tessier, Russ Schmit, Herman

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acm/sigda twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

ACM/SIGDA twelfth ACM international symposium on field-progr...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

The proceedings contains 24 papers from the acm/sigda international symposium on field programmable gate arrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluation of low leakage design techniques for field programmable gate arrays;reducing leakage energy in FPGAs using region constrained placement;an embedded true random number generator for FPGAs;a synthesis oriented omniscient manual editor;nanowire-based sublithographic programmable logic arrays;and highly pipelined asynchronous FPGAs.

关键词： field programmable gate arrays

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A 2005 review of FPGA arithmetic

A 2005 review of FPGA arithmetic

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Simard, Stéphane Beguenane, Rachid Larouche, Éric Morin, Luc ERMETIS Research Group Université du Québec à Chicoutimi Chicoutimi Que. G7H 2B1 Canada Novakod Technologies Inc. 930 Jacques Cartier Est Chicoutimi Que. G7H 7K9 Canada

This article is a concise literature review of the actual state of the art in arithmetic for field-programmable gate arrays (FPGAs), including studies, implementation techniques, operators, and structures, in various area-time tradeoffs. It covers the integer operations of addition/subtraction, multiplication, squaring, division, and square root, in parallel, and in both serial modes (least-significant digit first, and online). Many people, including researchers in the field of computer arithmetic, parallel computing, digital signal and image processing, system-on-a-programmable chip (SoPC) designers, and other people with a need to implement special purpose arithmetic circuits on FPGAs, might find such a review useful, either as an introduction to the topic, as a knowledge update, or for reference.

关键词： field programmable gate arrays

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