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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是401-410 订阅

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An FPGA generator for multipoint distributed random variables

An FPGA generator for multipoint distributed random variable...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Liberati, Nicola Bruti Platen, Eckhard Martini, Filippo Piccardi, Massimo School of Finance and Economics Department of Mathematical Sciences University of Technology Sydney Australia Faculty of Information Technology University of Technology Sydney Australia

Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differential equations. In applications such as finance, where "real time" execution is required, there is a strong need for highly efficient implementations. In this paper a fast and flexible dedicated hardware solution on a field programmable gate Array (FPGA) is presented. A comparative performance analysis between a software-only and the proposed hardware solution demonstrates that the FPGA solution is bottleneck-free, retains the flexibility of the software solution and significantly increases the computational efficiency.

关键词： field programmable gate arrays

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The effect of post-layout pin permutation on timing 05

The effect of post-layout pin permutation on timing

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Ding, Yuzheng Suaris, Peter Chou, Nanchi Mentor Graphics Corporation 8005 Boeckman Road Wilsonville OR 97070 United States

ISBN: (纸本)9781595930293

In this paper we study the effect of post-layout pin permutation of designs for FPGA devices with non-uniform cell delays. We present a simple, but timing optimal, pin permutation scheme, and report the results of applying the scheme on a set of public logic synthesis benchmark designs that were synthesized and placed by state-of-the-art commercial FPGA design tools configured to maximum optimization level. Despite the preceding optimizations, we still observed an average timing improvement of 3.7%. This demonstrates the importance of fully utilizing non-uniform cell delays during design optimizations for modern FPGA devices and the still presenting potential of improvement. Copyright 2005 acm.

关键词： field programmable gate arrays

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Design of programmable interconnect for sublithographic programmable logic arrays 05

Design of programmable interconnect for sublithographic prog...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： DeHon, André Dept. of CS 256-80 California Institute of Technology Pasadena CA 91125 United States

ISBN: (纸本)9781595930293

Sublithographic programmable Logic arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional lithographic patterning, we show how modestsized PLA logic blocks, which are efficient for implementing logic, can be organized into a segmented, Manhattan mesh interconnection scheme. The resulting programmable architecture has a macro-scale view which is reminiscent of lithographic FPGA and CPLD designs despite the fact that the low-level, sublithographic fabrication techniques used are much more highly constrained than conventional lithography and are prone to high defect rates. Using the Toronto 20 benchmark set, we begin to explore the design space for these sublithographic architectures and show that they may allow us to exploit nanowire building blocks to reach one to two orders of magnitude greater density than 22nm CMOS lithography. Copyright 2005 acm.

关键词： programmable logic controllers

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Dynamic reconfiguration in FPGA-based SoC designs

Dynamic reconfiguration in FPGA-based SoC designs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Bartosinski, Roman Daněk, Martin Honzik, Petr Matoušek, Rudolf Inst. of Information Theory and Automatioru Czech Academy of Sciences Pod vodarenskou vezi 4 182 08 Praha 8 Czech Republic

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable FPGA to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family FPGAs and the Atmel FPSLIC family FPGAs - is compared in terms of resource requirements, operating frequency, and power consumption.

关键词： field programmable gate arrays

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Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs 05

Analysis of yield loss due to random photolithographic defec...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Campregher, Nicola Cheung, Peter Y. K. Vasilko, Milan Constantinides, George A. Electrical and Electronic Engineering Imperial College London United Kingdom School of Design Engineering and Computing Bournemouth University United Kingdom

ISBN: (纸本)9781595930293

This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers. A proven yield model is adapted to target the FPGA interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented. Copyright 2005 acm.

关键词： field programmable gate arrays

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Automated synthesis for asynchronous FPGAs 05

Automated synthesis for asynchronous FPGAs

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Peng, Song Fang, David Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States Advanced Microelectronics Department Sandia National Laboratories United States

ISBN: (纸本)9781595930293

Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Copyright 2005 acm.

关键词： field programmable gate arrays

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Figaro: An automatic tool flow for designs with dynamic reconfiguration

Figaro: An automatic tool flow for designs with dynamic reco...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Nasi, Kelly Daněk, Martin Karoubalis, Theodoras Pohl, Zdeněk Atmel Hellas S.A. Papazachariou 48 GR 17342 Ag. Dimitros Athens Greece Inst. of Information Theory and Automation Czech Academy of Sciences Pod vodarenskou vezi 4 182 08 Praha 8 Czech Republic

Although runtime dynamic reconfiguration of the FPGA devices has been an issue of the last decade, it has yet to achieve general recognition by the design community. The reasons for this are clear;there exists no straightforward design methodology, and the partitioning and CAD tool support is poor. This paper presents general concepts implemented in a placement and routing tool that provides an environment where designs that are partially and dynamically reconfigurable can be processed in order to be implemented on FPGAs that support this technology, such as the Armel AT40K and AT94K series. The function of the tool is demonstrated on a simple real-world example.

关键词： field programmable gate arrays

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A petri-net based pre-runtime scheduler for dynamically self-reconfiguration of FPGAs

A petri-net based pre-runtime scheduler for dynamically self...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Eskinazi, Remy De Lima, Manoel E. Maciel, Paulo R. M. Valderrama, Carlos A. Filho, Abel G. Nascimento, Paulo S. B. Polytechnic School University of the State of Pernambuco Informatics Center Computer Engineering Group Federal University of Pernambuco

Dynamically Reconfigurable Systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes a Petri Net based methodology for the design of dynamically reconfigurable systems, where tasks scheduling has as prime objective the best temporal performance of the overall application. The methodology includes the generation of an embedded controller supporting the scheduling process in the target architecture.

关键词： field programmable gate arrays

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Soft error rate estimation and mitigation for SRAM-based FPGAs 05

Soft error rate estimation and mitigation for SRAM-based FPG...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Asadi, Ghazanfar Tahoori, Mehdi B. Northeastern University Dept. of Electrical and Computer Engineering Boston MA 02115 United States

ISBN: (纸本)9781595930293

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods. In this paper, we present an analytical approach to estimate the failure rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of FPGA-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs. Copyright 2005 acm.

关键词： field programmable gate arrays

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HARP: Hard-wired routing pattern FPGAs

HARP: Hard-wired routing pattern FPGAs

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Sivaswamy, Satish Wang, Gang Ababei, Cristinel Bazargan, Kia Kastner, Ryan Bozorgzadeh, Eli ECE Dept. Univ. of Minnesota Minneapolis MN 55455 Dept. of ECE Univ. of California Santa Barbara Santa Barbara CA 93106 Computer Science Dept. Univ. of California Irvine Irvine CA 92697

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture1 that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%. Copyright 2005 acm.

关键词： field programmable gate arrays

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