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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 628 条记录，以下是431-440 订阅

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Efficient packet classification for network intrusion detection using FPGA 05

Efficient packet classification for network intrusion detect...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Song, Haoyu Lockwood, John W. Department of CSE Washington University St. Louis United States

ISBN: (纸本)9781595930293

FPGA technology has become widely used for real-time network intrusion detection. In this paper, a novel packet classification architecture called BV-TCAM is presented, which is implemented for an FPGA-based Network Intrusion Detection System (NIDS). The classifier can report multiple matches at gigabit per second network link rates. The BV-TCAM architecture combines the Ternary Content Addressable Memory (TCAM) and the Bit Vector (BV) algorithm to effectively compress the data representations and boost throughput. A tree-bitmap implementation of the BV algorithm is used for source and destination port lookup while a TCAM performs the lookup of the other header fields, which can be represented as a prefix or exact value. The architecture eliminates the requirement for prefix expansion of port ranges. With the aid of a small embedded TCAM, packet classification can be implemented in a relatively small part of the available logic of an FPGA. The design is prototyped and evaluated in a Xilinx FPGA XCV2000E on the FPX platform. Even with the most difficult set of rules and packet inputs, the circuit is fast enough to sustain OC48 traffic throughput. Using larger and faster FPGAs, the system can work at speeds greater than OC192. Copyright 2005 acm.

关键词： field programmable gate arrays

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Dual-Vt FPGA design for leakage power reduction

Dual-Vt FPGA design for leakage power reduction

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Kumar, Akhilesh Anis, Mohab Electrical and Computer Engineering University of Waterloo Waterloo Ont. N2L 3G1

Leakage power has been overshadowed by dynamic power minimization techniques in FPGAs, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the FPGA architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the FPGA for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the FPGA architecture. Results indicate that over 95% of the logic elements in the FPGA can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of FPGA can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.

关键词： field programmable gate arrays

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Skew-programmable clock design for FPGA and skew-aware placement 05

Skew-programmable clock design for FPGA and skew-aware place...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Yeh, Chao-Yang Marek-Sadowska, Malgorzata ECE Department University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781595930293

In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for programming PDEs to optimize timing. Unlike previous methods for FPGA skew optimization which require large power and routing penalty, our method can achieve large timing improvement with small overhead. Typically, if timing requirements are tight, placers make efforts to satisfy them, often at a cost of compromising routability, total wire length, and power. In this work, we propose novel clock-skew-aware placement algorithms which allow us to relax the timing constraints during placement. Timing can be later optimized as a post process. Even though we demonstrate the efficiency of our approach using FPGAs, the new skew optimization method and the new placement algorithm are quite general and can be applied to any general, topology-constrained skew optimization problem. Experimental results indicate that using the new clock-architecture we can obtain a 22% timing improvement for post-layout skew optimization and an additional 21% improvement from our skew-aware placement algorithm. In one fabric, the cost of added logic is 2.19% as measured by dynamic power dissipation, and 0.85% in terms of area overhead. Copyright 2005 acm.

关键词： field programmable gate arrays

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Domain specific non-uniform routing architecture for embedded programmable IP core 05

Domain specific non-uniform routing architecture for embedde...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Wen, Yujie Tong, Jiarong Chiang, Charles State Key Lab of ASIC and System Fudan University Shanghai China Synopsys Inc. Mountain View CA 94043

ISBN: (纸本)9781595930293

Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical FPGA model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.

关键词： Embedded systems

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Efficient utilization of heterogeneous routing resources for FPGAs

Efficient utilization of heterogeneous routing resources for...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Rautela, Deepak Katti, Rajendra Department of Electrical and Computer Engineering North Dakota State University Fargo ND 58105

The routing resources available in recent FPGA architectures (e.g., Xilinx Virtex-II) are very different from the older generation of FPGAs (e.g., Xilinx XC4000). The latest FPGA architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectivity. Most of the FPGA routing algorithms have been implemented on XC4000 style architectures and not much work has been reported for architectures with directly driven heterogeneous routing resources. Since routing resources in FPGAs are fixed, it is very important for the routing algorithms to fully exploit the potential of new routing architectures. FPGA routing architectures are usually represented as a routing resource graph (RRG). The construction of RRG to accurately model all the routing resources of current FPGA architectures is not a trivial task. In this paper we present a simplified scheme to build the RRG for FPGA architectures with heterogeneous routing resources. Using our RRG construction scheme we have built a routability driven detailed FPGA router named "Bison". We also present a dynamic weight update based heuristic which we have incorporated into the router, so that efficient utilization of routing resources can be achieved.

关键词： field programmable gate arrays

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Soft multiprocessor systems for network applications

Soft multiprocessor systems for network applications

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Jin, Yujia Plishker, William Ravindran, Kaushik Satish, Nadathur Keutzer, Kurt Electrical Engineering and Computer Sciences UC Berkeley Berkeley CA 94709

Modem network applications require devices that provide high-performance at gigabit line rates with the flexibility to support diverse application standards and services. However, prohibitive product design costs and shrinking market windows restrict the number of ASIC/ASSP design starts to only selective application niches. The FPGA is an alternate cost-effective medium for many applications. However, creating a system solution through programming an FPGA with an HDL is only attractive to few application developers. Designers would prefer a software solution if it can meet their design constraints. An alterative is an FPGA-based soft multiprocessor system: a programmable multiprocessor on the FPGA composed of a network of hard and soft processing cores. Soft multiprocessors provide a software-level abstraction for programming an FPGA. In this study, we evaluate the feasibility and effectiveness of soft multiprocessor systems. We compare a soft multiprocessor implementation against FPGA hardware and an ASSP implementation for two network applications: IPv4 packet forwarding and Network Address Translation (NAT). Our study indicates that soft multiprocessors lose only a factor of 2X in performance compared to a custom ASSP, while providing great savings in terms of silicon development costs. Moreover, the presence of architectures and development environments for soft multiprocessor systems could open the FPGA market to the much larger world of embedded system software designers.

关键词： field programmable gate arrays

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Mapping algorithm for large-scale field programmable analog array

Mapping algorithm for large-scale field programmable analog ...

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2005 international symposium on Physical Design, ISPD'05

作者： Baskaya, Faik Reddy, Sasank Lim, Sung Kyu Hall, Tyson Anderson, David V. School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332 United States

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With these advances, analog circuits and systems can be programmable, reconfigurable, adaptive, implemented on standard CMOS to take advantage of scaled CMOS technology, and at a density comparable to digital memories. Our goal in this paper is to develop the first physical design automation toolset for floating-gate based FPAA with focus on minimization of parasitic effects on FPAA interconnect. We provide graph-based analog circuit and FPAA device modeling suitable for efficient mapping. Our FPAA clustering algorithm constructs Computational Analog Blocks (CAB) from analog circuit elements while improving the utilization of the device and reducing its impact on the total number of routing switches used. Experimental results demonstrate the effectiveness of our approach. Copyright 2005 acm.

关键词： field programmable gate arrays

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64-bit floating-point FPGA matrix multiplication 05

64-bit floating-point FPGA matrix multiplication

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Dou, Yong Vassiliadis, S. Kuzmanov, G.K. Gaydadjiev, G.N. National Laboratory for Parallel and Distributed Processing Changsha 410073 China Computer Engineering EEMCS TU Delft P.O. Box 5031 2600 GA Delft Netherlands

ISBN: (纸本)9781595930293

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth. Copyright 2005 acm.

关键词： field programmable gate arrays

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Sparse matrix-vector multiplication on FPGAs 05

Sparse matrix-vector multiplication on FPGAs

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Zhuo, Ling Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los Angeles CA 90089-2560 United States

ISBN: (纸本)9781595930293

Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices significantly reduces the performance of SpMXV on general-purpose processors, which rely heavily on the cache hierarchy to achieve high performance. The abundant hardware resources on current FPGAs provide new opportunities to improve the performance of SpMXV. In this paper, we propose an FPGA-based design for SpMXV. Our design accepts sparse matrices in Compressed Row Storage format, and makes no assumptions about the sparsity structure of the input matrix. The design employs IEEE-754 format double-precision floating-point multipliers/adders, and performs multiple floating-point operations as well as I/O operations in parallel. The performance of our design for SpMXV is evaluated using various sparse matrices from the scientific computing community, with the Xilinx Virtex-II Pro XC2VP70 as the target device. The MFLOPS performance increases with the hardware resources on the device as well as the available memory bandwidth. For example, when the memory bandwidth is 8 GB/s, our design achieves over 350 MFLOPS for all the test matrices. It demonstrates significant speedup over general-purpose processors particularly for matrices with very irregular sparsity structure. Besides solving SpMXV problem, our design provides a parameterized and flexible tree-based design for floating-point applications on FPGAs. Copyright 2005 acm.

关键词： field programmable gate arrays

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Accelerating mutual information-based 3D medical image registration with an FPGA computing platform

Accelerating mutual information-based 3D medical image regis...

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acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Li, Jianchun Papachristou, Christos Shekhar, Raj Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH 44106 Department of Radiology University of Maryland Baltimore MD 21201

Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like many other 3D imaging algorithms, 3D registration needs to process vast amount of image data. The intrinsic computing characteristics of the mutual information-based registration algorithm make it even more difficult to manage and cache the input data. In this paper, we introduce our FPGA-based computing platform and detail its application in accelerating the mutual information-based 3D image registration. This platform is designed to accelerate a series of 3D medical imaging algorithms dominated by local operations. It is a System-on-Chip (SoC) architecture with an intelligent data caching system for efficient data fetching and buffering. A reconfigurable multi-pipeline execution unit in the platform is designed to perform high-speed parallel computation. This unit can be customized according to different algorithm requirements to achieve high performance. The simulation results for accelerating the mutual information based registration with our platform show that a speed-up of about 30 can be achieved when compared to a single-CPU computer. Moreover, the platform can be easily reconfigured to accelerate other 3D medical imaging algorithms.

关键词： field programmable gate arrays

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