检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

597 篇 会议
32 篇 期刊文献

馆藏范围

629 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

534 篇 工学
- 480 篇 计算机科学与技术...
- 281 篇 软件工程
- 219 篇 电子科学与技术（可...
- 170 篇 电气工程
- 91 篇 信息与通信工程
- 33 篇 动力工程及工程热...
- 33 篇 控制科学与工程
- 27 篇 机械工程
- 16 篇 生物工程
- 14 篇 建筑学
- 12 篇 仪器科学与技术
- 10 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 生物医学工程（可授...
- 6 篇 材料科学与工程（可...
- 5 篇 光学工程
- 3 篇 测绘科学与技术
201 篇 理学
- 165 篇 数学
- 35 篇 物理学
- 20 篇 统计学（可授理学、...
- 17 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
55 篇 管理学
- 47 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
15 篇 经济学
- 15 篇 应用经济学
11 篇 法学
- 9 篇 社会学
4 篇 艺术学
- 4 篇 设计学（可授艺术学...
3 篇 农学
2 篇 教育学

主题

285 篇 field programmab...
169 篇 field programmab...
50 篇 signal processin...
50 篇 clocks
49 篇 modulation
49 篇 ofdm
49 篇 estimation
49 篇 filtration
30 篇 fpga
8 篇 field-programmab...
7 篇 fpgas
7 篇 logic gates
7 篇 systolic arrays
7 篇 optimization
7 篇 switches
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...
6 篇 routing

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 nanyang technol ...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
10 篇 chen deming
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

622 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 629 条记录，以下是521-530 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Timing-driven routing for FPGAs based on Lagrangian relaxation

Timing-driven routing for FPGAs based on Lagrangian relaxati...

引用

ISPD-2002: international symposium on Physical Design

作者： Lee, Seokjin Wong, D.F. Dept. of Electrical and Comp. Eng. University of Texas at Austin Austin TX 78712 United States

As interconnection delay plays an important role in determining circuit performance in FPGAs, timing-driven FPGA routing has received much attention recently. In this paper, we present a new timing-driven routing algorithm for FPGAs. The algorithm finds a routing with minimum critical path delay for a given placed circuit using the Lagrangian relaxation technique. Lagrangian multipliers used to relax timing constraints are updated by subgradient method over iterations. Incorporated into the cost function, these multipliers guide the router to construct routing tree for each net. During routing, the exclusivity constraints on each routing resources are also taken care of to route circuits successfully. Experimental results on benchmark circuits show that our approach outperforms the state-of-the-art VPR router.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Constrained clock shifting for field programmable gate arrays 02

Constrained clock shifting for field programmable gate array...

引用

proceedings of the 2002 acm/sigda tenth international symposium on field-programmable gate arrays

作者： Deshanand P. Singh Stephen D. Brown University of Toronto Toronto Canada

ISBN: (纸本)9781581134520

Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting optimization techniques to improve the clock frequency as a post place and route *** Shifting Optimization is a technique first formalized in [4]. It is a cycle-stealing algorithm that allows one to reduce the critical path delay of a synchronous circuit by shifting the clock signals at each register. This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register. Typical FPGAs contain a number of special purpose global clock networks that distribute clock signals to every register in the chip. Unused global clock lines in FPGAs can be used to distribute a finite set of clock skews to the entire circuit. We propose an efficient integer programming method to find the optimal circuit improvement for a finite set of clock skews. This technique is modified to consider inherent uncertainties present in the timing models. The uncertainty controls the aggressiveness of the optimizations as we must take great care in ensuring functionality for any range of possible timing *** results confirm intuition that more aggressive speed optimizations can be performed as timing models become more accurate. We also show that providing 4 skewed versions of the nominal clock signal results in the best delay--area tradeoff. This result is evocative as it may suggest future FPGA architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater pow

关键词：

来源：评论

学校读者我要写书评

暂无评论

Is marriage in the cards for programmable logic, microprocessors and ASICs?

Is marriage in the cards for programmable logic, microproces...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Anon

来源：评论

学校读者我要写书评

暂无评论

Simultaneous logic decomposition with technology mapping in FPGA designs 01

Simultaneous logic decomposition with technology mapping in ...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Chen, G. Cong, J. Computer Science Department University of California Los Angeles CA 90095 United States

ISBN: (纸本)9781581133417

Conventional technology mapping algorithms for SRAM-based field programmable gate arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. Our study leads to two conclusions: (1) For depth minimization, the best algorithms in conventional flow (dmig + CutMap) produce satisfactory results with a short runtime, even with a fixed decomposition;(2) When all the structural decompositions of the 6-bounded Boolean network are explored, SLDMap consistently outperforms the state-of-the-art separate flow (dmig + CutMap) by 12% in depth and 10% in area on average;it also consistently outperforms the state-of-the-art combined approach dogma by 8% in depth and 6% in area on average.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A memory coherence technique for online transient error recovery of FPGA configurations 01

A memory coherence technique for online transient error reco...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Huang, W.-J. McCluskey, E.J. Center for Reliable Computing Department of Electrical Engineering Stanford University Stanford CA 94305-4055 United States

ISBN: (纸本)9781581133417

The partial reconfiguration feature of some of the current-generation field programmable gate arrays (FPGAs) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Interconnect pipelining in a throughput-intensive FPGA architecture 01

Interconnect pipelining in a throughput-intensive FPGA archi...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Singh, A. Mukherjee, A. Marek-Sadowska, M. Department of Electrical Engineering University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781581133417

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, circuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput FPGA architecture based on the wavesteering design principle to handle throughput-intensive applications. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconnect scheme to support the strict timing requirements that is necessitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this FPGA fabric shows an increasing throughput performance.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

An FPGA-based video compressor for H.263 compatible bit streams 01

An FPGA-based video compressor for H.263 compatible bit stre...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lienhart, G. Männer, R. Lay, R. Noffz, K.H. Dept. for Computer Science V University of Mannheim D-68131 Mannheim Germany

ISBN: (纸本)9781581133417

This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

LRoute: A delay minimal router for hierarchical CPLDs 01

LRoute: A delay minimal router for hierarchical CPLDs

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lee, K.K. Wong, M.D.F. Synopsys Inc. 700 E. Middlefield Rd Mountain View CA 94043 United States

ISBN: (纸本)9781581133417

This paper describes LRoute, a novel router for the popular and scalable hierarchical Complex programmable Logic Devoices (CPLDs). CPLD routing has constraints om routing topologies due to architectural limitations and performance considerations. These constraints make the problem quite different from FPGA routing and render the routing problem more complicated. Extensions of popular FPGA routers like the maze router performs poorly on such CPLDs. There is also little published work on CPLD routing. LRoute uses a different paradigm based on the Lagrangian Relaxation framework in the theory of mathematical programming. It respects the topology constraints imposed and routes a circuit with minimum delay. We tested this router on a set of industry problems that commercial software failed to route. Our router was able to route all of them very quickly.

关键词： programmable logic controllers

来源：评论

学校读者我要写书评

暂无评论

Configuration compression for FPGA-based embedded systems 01

Configuration compression for FPGA-based embedded systems

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Dandalis, A. Prasanna, V.K. Electrical Engineering - Systems University of Southern California 3740 McClintock Avenue Los Angeles CA 90089-2562 United States

ISBN: (纸本)9781581133417

FPGAs are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, the cost-effectiveness of FPGA-based embedded systems is significantly affected by the memory required for storing various FPGA configurations. This paper proposes a novel compression technique that reduces the memory required for storing FPGA configurations and results in high decompression efficiency. Decompression efficiency corresponds to the decompression hardware cost as well as the decompression rate. The proposed technique is applicable to any SRAM-based FPGA device since configuration bit-streams are processed as raw data. The required decompression hardware is simple and is independent of the individual semantics of configuration bit-streams or specifc features of the on-chip configuration mechanism. Moreover, the time to configure the device is not affected by our compression technique. Using our technique, we demonstrate up to 41% savings in memory for configuration bit-streams of several real-world applications.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Matching and searching analysis for parallel hardware implementation on FPGAs 01

Matching and searching analysis for parallel hardware implem...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Moisset, P. Diniz, P. Park, J. University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States

ISBN: (纸本)9781581133417

Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a simple search/matching predicate. Their inherent sequential nature, either because of data dependences but more often because of very strong control dependences, makes it impossible to apply existing data dependence and parallelization analysis to exploit significant levels parallelism on traditional architectures. This paper describes a class of searching and matching computations and describes a mapping strategy to map these computations to hardware. We have developed a compiler analysis in SUIF using array data dependence analysis and implicit loop unrolling analysis to expose more parallelism for the parallel evaluation of these computations. Our compiler generates parallel hardware specifications in VHDL. The resulting parallel hardware yields significant performance improvements when these kernel operators are repeated over shifted portions of the input data on FPGA-based computing architectures.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共63页 << < 49 50 51 52 53 54 55 56 57 58 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：