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Performance-driven mapping for CPLD architectures 01

Performance-driven mapping for CPLD architectures

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Chen, D. Cong, J. Ercegovac, M.D. Huang, Z. Department of Computer Science University of California Los Angeles CA 90095 United States

ISBN: (纸本)9781581133417

In this paper we present a performance-driven mapping algorithm, PLAmap, for CPLD architectures which consist of a large number of PLA-style logic cells. The primary goal of our mapping algorithm is to minimize the depth of the mapped circuit. Meanwhile, we have successfully reduced the area of the mapped circuits by applying several heuristic techniques, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA-packing. We compare our PLAmap with a recently-published algorithm TEMPLA [1] and a commercial tool, Altera's MAX+PLUS II [16]. Experimental results on various MCNC benchmarks show that overall TEMPLA uses 8 to 11% less area at the cost of 96 to 106% more mapping depth, and MAX+PLUS II uses 12% less area but 58% more delay compared with our mapper.

关键词： programmable logic controllers

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Reprogrammable network packet processing on the field programmable Port Extender (FPX) 01

Reprogrammable network packet processing on the Field Progra...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lockwood, J.W. Naufel, N. Turner, J.S. Taylor, D.E. Department of Computer Science Applied Research Lab. Washington University 1 Brookings Drive Saint Louis MO 63130 United States

ISBN: (纸本)9781581133417

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the field programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two field programmable gate arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules. Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA. Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.

关键词： Packet networks

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The case for registered routing switches in field programmable gate arrays 01

The case for registered routing switches in field programmab...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Singh, D.P. Brown, S.D. Department of Electrical Engineering University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581133417

FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. The goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. This rescheduling would not effect the timing of the visible outputs (no latency is added to the overall system). Specifically, we analyze the effects of adding a small number of registered routing switches to an FPGA architecture with segmented routing resources. A parameterized FPGA architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in FPGA architectures. Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.

关键词： field programmable gate arrays

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Timing-driven placement for hierarchical programmable logic devices 01

Timing-driven placement for hierarchical programmable logic ...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Hutton, M. Adibsamii, K. Leaver, A. Altera Corporation 101 Innovation Drive San Jose CA 95134 United States

ISBN: (纸本)9781581133417

In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures. Our algorithm follows the natural recursive k-way partitioning-based approach to placement on such devices. Our contributions include a specification of the overall TDC (timing-driven compilation) algorithm, an analysis of heuristics such as a variant of multi-start partitioning, a new method for adaptive delay computation, and a discussion of the structure of critical paths and sub-graphs on modern PLD designs. This algorithm has been implemented in a production quality commercial tool, and we report on the results with and without the implementation of the new techniques. The basic result is a substantial 38.5% average (36.3% median) improvement in register-to-register performance across a range of real designs in modern density ranges, at a cost of approximately 3.65X average (2.88X median) place-and-route CPU time. (These improvements and costs are relative to the same tool prior to the efforts described in this paper.) A partial implementation of the new algorithm shows approximately half the performance gain, with approximately half the compile time cost.

关键词： programmable logic controllers

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Detailed routing architectures for embedded programmable logic IP cores 01

Detailed routing architectures for embedded programmable log...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Hallschmid, P. Wilton, S.J.E. Department of Electrical Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581133417

As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small;for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.

关键词： Application specific integrated circuits

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Runtime and quality tradeoffs in FPGA placement and routing 01

Runtime and quality tradeoffs in FPGA placement and routing

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Mulpuri, C. Hauck, S. Department of Electrical Engineering University of Washington Seattle WA 98195 United States

ISBN: (纸本)9781581133417

Many applications of FPGAs, especially logic emulation and custom computing, require the quick placement and routing of circuit designs. In these applications, the advantages FPGA-based systems have over software simulation are diminished by the long run-times of current CAD software used to map the circuit onto FPGAs. To improve the run-time advantage of FPGA systems, users may be willing to trade some mapping quality for a reduction in CAD tool runtimes. In this paper, we seek to establish how much quality degradation is necessary to achieve a given runtime improvement. For this purpose, we implemented and investigated numerous placement and routing algorithms for FPGAs. We also developed new tradeoff-oriented algorithms, where a tuning parameter can be used to control this quality vs. runtime tradeoff. We show how different algorithms can achieve different points within this tradeoff spectrum, as well as how a single algorithm can be tuned to form a curve in the spectrum. We demonstrate that the algorithms vary widely in their tradeoffs, with the fastest algorithm being 8x faster than the slowest, and the highest quality algorithm being 5x better than the least quality algorithm. Compared to the commercial Xilinx CAD tools, we can achieve a 3x speed-up by allowing 1.27x degradation in quality, and a factor of 1.6x quality improvement with 2x slowdown.

关键词： field programmable gate arrays

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Algorithmic transformations in the implementation of K-means clustering on reconfigurable hardware 01

Algorithmic transformations in the implementation of K-means...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Estlick, M. Leeser, M. Theiler, J. Szymanski, J.J. Department of Electrical Engineering Northeastern University Boston MA United States

ISBN: (纸本)9781581133417

In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that dramatically increased the achievable parallelism. We apply the k-means algorithm to multi-spectral and hyper-spectral images, which have tens to hundreds of channels per pixel of data. K-means is an iterative algorithm that assigns assigns to each pixel a label indicating which of K clusters the pixel belongs to. K-means is a common solution to the segmentation of multi-dimensional data. The standard software implementation of k-means uses floating-point arithmetic and Euclidean distances. Floating point arithmetic and the multiplication-heavy Euclidean distance calculation are fine on a general purpose processor, but they have large area and speed penalties when implemented on an FPGA. In order to get the best performance of k-means on an FPGA, the algorithm needs to be transformed to eliminate these operations. We examined the effects of using two other distance measures, Manhattan and Max, that do not require multipliers. We also examined the effects of using fixed precision and truncated bit widths in the algorithm. It is important to explore algorithmic level transforms and tradeoffs when mapping an algorithm to reconfigurable hardware. A direct translation of the standard software implementation of k-means would result in a very inefficient use of FPGA hardware resources. Analysis of the algorithm and data is necessary for a more efficient implementation. Our resulting implementation exhibits approximately a 200 times speed up over a software implementation.

关键词： field programmable gate arrays

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Mixing buffers and pass transistors in FPGA routing architectures 01

Mixing buffers and pass transistors in FPGA routing architec...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Sheng, M. Rose, J. Department of Electrical Engineering University of Toronto Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781581133417

The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the interconnection of the switches and wires. FPGA routing architecture has a major influence on the logic density and speed of FPGA devices. Previous work [1] based on a 0.35um CMOS process has suggested that an architecture consisting of length 4 wires (where the length of a wire is measured in terms of the number of logic blocks it passes before being switched) and half of the programmable switches are active buffers, and half are pass transistors. In that work, however, the topology of the routing architecture prevented buffered tracks from connecting to pass-transistor tracks. This restriction prevents the creation of interconnection trees for high fanout nets that have a mixture of buffers and pass transistors. Electrical simulations suggest that connections closer to the leaves on interconnection trees are faster using pass transistors, but it is essential to buffer closer to the source. This latter effect is well known in regular ASIC routing [2]. In this work we propose a new routing architecture that allows liberal switching between buffered and pass transistor tracks. We explore various versions of the architecture to determine the density-speed trade-off. We show that one version of the new architecture results in FPGAs with 10% faster critical path delay yet uses the same area as the previous architecture that does not allow such switching. We also show that the new architecture allows a useful area-speed trade off and several versions of the new architecture result in FPGAs with 8% gain in area-delay product than the previous architecture that does not allow the switching.

关键词： field programmable gate arrays

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Physical design for FPGAs 01

Physical design for FPGAs

引用

2001 international symposium on Physical Design

作者： Jayaraman, R. Xilinx Inc. 2100 Logic Drive San Jose CA 95131 United States

ISBN: (纸本)9781581133479

FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements and challenges. Consequently the algorithms in FPGA physical design have evolved differently from their ASIC counterparts. Apart from allowing FPGA users to implement their designs on FPGAs, FPGA physical design is also used extensively in developing and evaluating new FPGA architectures. Finally, the future of FPGA physical design is discussed along with how it is interacting with the latest FPGA technologies.

关键词： field programmable gate arrays

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Evaluation of the streams-C C-to-FPGA compiler: An applications perspective 01

Evaluation of the streams-C C-to-FPGA compiler: An applicati...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Frigo, J. Gokhale, M. Lavenier, D. Los Alamos National Laboratory Los Alamos NM 87545 United States

ISBN: (纸本)9781581133417

The Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. The Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. The processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated. The Streams-C language and compiler offer a very high level of expressivity for reconfigurable computing application development, particularly for stream-processing applications. We find this is reflected in productivity, for a factor of up to 10 times improvement in time to produce a program. However, use of the tool in the "real world" is predicated on performance: only if such a compiler can deliver performance comparalble to hand-coded performance will it be used in practice. This paper presents an application study of the Streams-C compiler. Four applications have been written in Streams-C and compiled to the AMC Wildforce board containing Xilinx 4036's. Those same applications have been hand-coded in a combination of RTL and structural VHDL. We compare performance of the generated code with the hand-optimized code. Our study shows that the compiler-generated designs are 1.37-4 times the area and 1/2-1 times the clock frequency of the hand designs. We find that the compiler, based on the SUIF infrastructure, can be greatly improved through various standard compiler optimizations that are not currently being exploited. Thus we are currently rewriting a public domain version of Streams-C to better optimize and target the Virtex chip.

关键词： field programmable gate arrays

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