The proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA sys...
详细信息
The proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA systems & other reprogrammable architectures;partitioning and floor planning for FPGAs;fault detection and fault tolerance for FPGAs;fast computer aided design (CAD) tools for FPGAs;time multiplexed FPGAs;FPGAs with embedded memory;and programmable architectures with special features.
Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfi...
详细信息
Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.
An approach for runtime mapping is proposed that utilizes self-reconfigurability of multicontext fieldprogrammablegatearrays (FPGA) to achieve very high speedups over existing approaches. The idea is to design and ...
详细信息
An approach for runtime mapping is proposed that utilizes self-reconfigurability of multicontext fieldprogrammablegatearrays (FPGA) to achieve very high speedups over existing approaches. The idea is to design and map logic onto a multicontext FPGA that in turn maps problem instance dependent logic onto other contexts of the same FPGA. As a result, computer aided design tools need to be used just once for each problem and not once for every problem instance as is usually done.
This paper describes the hardware implementation of the Generalized Profile Search algorithm using online arithmetic and redundant data representation. This is part of the GenStorm project, aimed at providing a dedica...
详细信息
This paper describes the hardware implementation of the Generalized Profile Search algorithm using online arithmetic and redundant data representation. This is part of the GenStorm project, aimed at providing a dedicated computer for biological sequence processing based on reconfigurable hardware using FPGAs. The serial evaluation of the result made possible by a redundant data representation leads to a significant increase of data throughput in comparison with standard non redundant data coding.
A new search-based satisfiability (SAT) formulation that can handle entire fieldprogrammablegate array (FPGA), routing all nets concurrently is presented. The approach relies on a recently developed SAT engine that ...
详细信息
A new search-based satisfiability (SAT) formulation that can handle entire fieldprogrammablegate array (FPGA), routing all nets concurrently is presented. The approach relies on a recently developed SAT engine that uses systematic search with conflict directed nonchronological backtracking, capable of handling very large SAT instances. Preliminary experimental results suggest that this approach to FPGA routing is more viable than earlier binary decision diagram-based method.
The placement phase of the compile process and an ultrafast placement algorithm targeted to fieldprogrammablegatearrays (FPGA) are presented. The algorithm is based on a combination of multiple-level, bottom-up clu...
详细信息
The placement phase of the compile process and an ultrafast placement algorithm targeted to fieldprogrammablegatearrays (FPGA) are presented. The algorithm is based on a combination of multiple-level, bottom-up clustering and hierarchical simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time. In addition, operating on its fastest mode, this tool can provide an accurate estimate of the wirelength achievable with good quality placement. This can be used in conjunction with a routing predictor, to determine the routability of a given circuit on a given FPGA device.
A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream alr...
详细信息
A FPGA configuration method named configuration cloning is developed to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the configuration bit-stream already resident in a FPGA. The method resulted in speed and power improvement over off-chip partial reconfiguration techniques, while not requiring additional interconnects and control hardware. Cloning requires only a small amount of hardware overhead. Digital signal processing applications are discussed to demonstrate the order of magnitude reductions in configuration time and power.
A reconfigurable architecture optimized for media processing, and based on 4-bit arithmetic logic unit (ALU) and interconnect is described. Together, these allow the area devoted to configuration bits and routing swit...
详细信息
A reconfigurable architecture optimized for media processing, and based on 4-bit arithmetic logic unit (ALU) and interconnect is described. Together, these allow the area devoted to configuration bits and routing switches to be about 50% of the area of the basic CHESS array, leaving the rest available for user-visible functional units. CHESS flexibility in application mapping is largely due to the ability to feed ALU with instruction streams generated within the array, generous provision of embedded block random access memory, and the ability to trade routing switches for small memories.
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual...
详细信息
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual port RAM. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.
暂无评论