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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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FracBNN: Accurate and fpga-efficient binary neural networks with fractional activations 21

FracBNN: Accurate and fpga-efficient binary neural networks ...

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2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Zhang, Yichi Pan, Junhao Liu, Xinheng Chen, Hongzheng Chen, Deming Zhang, Zhiru Cornell University Ithaca United States University of Illinois Urbana-Champaign Urbana United States Sun Yat-sen University China

ISBN: (纸本)9781450382182

Binary neural networks (BNNs) have 1-bit weights and activations. Such networks are well suited for FPGAs, as their dominant computations are bitwise arithmetic and the memory requirement is also significantly reduced. However, compared to start-of-the-art compact convolutional neural network (CNN) models, BNNs tend to produce a much lower accuracy on realistic datasets such as ImageNet. In addition, the input layer of BNNs has gradually become a major compute bottleneck, because it is conventionally excluded from binarization to avoid a large accuracy loss. This work proposes FracBNN, which exploits fractional activations to substantially improve the accuracy of BNNs. Specifically, our approach employs a dual-precision activation scheme to compute features with up to two bits, using an additional sparse binary convolution. We further binarize the input layer using a novel thermometer encoding. Overall, FracBNN preserves the key benefits of conventional BNNs, where all convolutional layers are computed in pure binary MAC operations (BMACs). We design an efficient FPGA-based accelerator for our novel BNN model that supports the fractional activations. To evaluate the performance of FracBNN under a resource-constrained scenario, we implement the entire optimized network architecture on an embedded FPGA (Xilinx Ultra96 v2). Our experiments on ImageNet show that FracBNN achieves an accuracy comparable to MobileNetV2, surpassing the best-known BNN design on FPGAs with an increase of 28.9% in top-1 accuracy and a 2.5x reduction in model size. FracBNN also outperforms a recently introduced BNN model with an increase of 2.4% in top-1 accuracy while using the same model size. On the embedded FPGA device, FracBNN demonstrates the ability of real-time image classification. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the international Space Station 23

Fault Detection on Multi COTS FPGA Systems for Physics Exper...

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Tim Oberschulte Jakob Marten Holger Blume Gottfried Wilhelm Leibniz University Hannover Hannover Germany

ISBN: (纸本)9781450394178

field-programmable gate arrays (FPGAs) in space applications come with the drawback of radiation effects, which inevitably will occur in devices of small process size. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which is planned to operate on the international Space Station for several years. A total of more than 100 FPGAs distributed in the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. Due to the large amount of devices in BECCAL, commercial off-the-shelf (COTS) FPGAs are used which are not radiation hardened. In this work, we detect and mitigate radiation effects in an application specific COTS-FPGA-based communication network. For that redundancy is integrated into the design while the firmware is optimized to stay within the FPGA's resource constraints. A redundant integrity checker module is developed which can notify preceding network devices about data and configuration bit errors. The firmware is evaluated by injecting faults into data and configuration registers in simulation and real hardware. The FPGA resource usage of the firmware is cut down by more than half, enabling the use of double modular redundancy for the switching fabric. Together with the triple modular redundancy protected integrity checker, this combination fully prevents silent data corruptions in the design as shown in simulations and by injecting faults in hardware using the Intel Fault Injection FPGA IP Core while staying in the resource limitation of a COTS FPGA.

关键词： fault detection commercial off-the-shelf space application

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FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know It 20

FPGAs will Never be the Same Again: How the Newest FPGA Arch...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Nijssen, Raymond Achronix Semicond Corp Santa Clara CA 95054 USA

ISBN: (纸本)9781450370998

Since the inception of FPGAs over 2 decades ago, the micro-architectures and macro-architectures of FPGAs across all FPGA vendors have been converging strongly to the point that comparable FPGAs from the main FPGA vendors had virtually the same use models, and the same programming models. User designs were getting easier to port from one vendor to the other with every generation. Recent developments in from different FPGA vendors targeting the most advanced semiconductor technology nodes are an abrupt and disruptive break from this trend, especially at the macro-architectural level.

关键词： FPGA Architectures heterogeneous programmable systems FPGA programming models

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Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks 23

Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural ...

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Enhao Tang Shun Li Yanxiang Zhu Jun Yu Kun Wang Fudan University Shanghai China New York University New York NY USA Fuzhou University Fuzhou China VeriMake Innovation Lab Nanjing China

ISBN: (纸本)9781450394178

Graph Neural Networks (GNNs) have outstanding performance on graph-structured data and have been extensively accelerated by field-programmable gate array (FPGA) in various ways. However, existing accelerators significantly lack flexibility, especially in the following two aspects: 1) Many FPGA-based accelerators only support one GNN model. 2) The processes of re-synthesizing and bitstream re-generating are very time-consuming for new GNN models. To this end, we propose a highly integrated FPGA-based overlay processor for general GNN accelerations named Graph-OPU. Regarding the data structure and operation irregularity, we customize the instruction sets to support irregular operation patterns in the inference process of GNN models. Then, we customize our datapath and optimize the data format in the microarchitecture to take full advantage of high bandwidth memory (HBM). Moreover, we design the computation module to ensure a unified and fully-pipelined process of sparse matrix multiplication (SpMM) and general matrix multiplication (GEMM). Users can avoid the process of FPGA reconfiguration or RTL regeneration for the newly invented GNN models. We implement the hardware prototype on Xilinx Alveo U50 and test the mainstream GNN models with 9 datasets. Graph-OPU can achieve an average of 435× and 18× speedup, while 2013× and 109× better energy efficiency, compared with the Intel I7-12700KF processor and NVIDIA RTX3090 GPU, respectively. To the best of our knowledge, Graph-OPU is the first in-depth study on FPGA-based general processors for GNN acceleration with high speedup and energy efficiency.

关键词： high bandwidth memory graph neural network field-programmable gate array overlay processor

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A scalable and robust hierarchical floorplanning to enable 24-hour prototyping for 100k-LUT FPGAs 21

A scalable and robust hierarchical floorplanning to enable 2...

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2021 acm international symposium on Physical Design, ISPD 2021

作者： Gore, Ganesh Tang, Xifan Gaillardon, Pierre-Emmanuel University of Utah Salt Lake CityUT United States

ISBN: (纸本)9781450383004

Physical design for field programmable gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of programmable Routing 20

Straight to the Point: Intra- and Intercluster LUT Connectio...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Nikolic, Stefan Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Lausanne Switzerland Intel Corp San Jose CA USA

ISBN: (纸本)9781450370998

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both within and across multiple clusters, can eschew the transistor delays of crossbars, connection blocks, and switch blocks. In this paper we investigate the usefulness of enhancing classical field-programmable gate Array (FPGA) architectures with direct connections between LUTs. We present an efficient algorithm for searching automatically the most interesting patterns of such direct connections. Despite our methods being fairly conservative and relying on the use of unmodified standard CAD tools, we obtain a 2.77% improvement of the geometric mean critical path delay of a standard benchmark set, with improvement ranging from -0.17% to 7.3% for individual circuits. As modest as these results may seem at first glance, we believe that they position direct connections between LUTs as a promising topic for future research. Extending this work with dedicated CAD algorithms and exploiting the increased possibilities for optimal buffering, diagonal routing, and pipelining could prove direct connections important to the continuation of performance improvement into next generation FPGAs.

关键词： intercluster architectural exploration fpga lut cluster interconnect pattern direct connection clb hardened connection search intracluster enumeration algorithm

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FPGA 2016 - proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International ...

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2016 acm/sigda international symposium on field-programmable gate arrays, FPGA 2016

ISBN: (纸本)9781450338561

The proceedings contain 32 papers. The topics discussed include: hyperpipelining of high-speed interface logic;agile co-design for a reconfigurable datacenter;throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks;going deeper with embedded FPGA platform for convolutional neural network;using stochastic computing to reduce the hardware requirements for a restricted Boltzmann machine classifier;a platform-oblivious approach for heterogeneous computing: a case study with Monte Carlo-based simulation for medical applications;physical design of 3D FPGAs embedded with micro-channel-based fluidic cooling;Boolean satisfiability-based routing and its application to Xilinx ultrascale clock network;and pitfalls and tradeoffs in simultaneous, on-chip FPGA delay measurement.

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that FPGAs may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the FPGA DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the FPGA's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators 23

A Flexible Toolflow for Mapping CNN Models to High Performan...

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Yongzheng Chen Gang Wu Northeastern University Shenyang China

ISBN: (纸本)9781450394178

There have been many studies on developing automatic tools for mapping CNN models onto FPGAs. However, challenges remain in designing an easy-to-use toolflow. First, the toolflow should be able to handle models exported from various deep learning frameworks and models with different topologies. Second, the hardware architecture should make better use of on-chip resources to achieve high performance. In this work, we build a toolflow upon Open Neural Network Exchange (ONNX) IR to support different DL frameworks. We also try to maximize the overall throughput via multiple hardware-level efforts. We propose to accelerate the convolution operation by applying parallelism not only at the input and output channel level, but also at the output feature map level. Several on-chip buffers and corresponding management algorithms are also designed to leverage abundant memory resources. Moreover, we employ a fully pipelined systolic array running at 400 MHz as the convolution engine, and develop a dedicated bus to implement the im2col algorithm and provide feature inputs to the systolic array. We generated 4 accelerators with different systolic array shapes and compiled 12 CNN models for each accelerator. Deployed on a Xilinx VCU118 evaluation board, the performance of convolutional layers can reach 3267.61 GOPS, which is 99.72% of the ideal throughput (3276.8 GOPS). We also achieve an overall throughput of up to 2424.73 GOPS. Compared with previous studies, our toolflow is more user-friendly. The end-to-end performance of the generated accelerators is also better than that of related work at the same DSP utilization.

关键词： field-programmable gate array (FPGA) toolflow convolutional neural network (CNN) systolic array memory management

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LUXOR: An FPGA logic cell architecture for eficient compressor tree implementations

LUXOR: An FPGA logic cell architecture for eficient compress...

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2020 acm/sigda international symposium on field-programmable gate arrays, FPGA 2020

作者： Rasoulinezhad, Seyed Ramin Siddhartha Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney Sydney2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

ISBN: (纸本)9781450370998

We propose two tiers of modiications to FPGA logic cell architecture to deliver a variety of performance and utilization beneits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modiications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modiications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of *** benchmarks beneit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-eicient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells. © 2020 Association for Computing Machinery.

关键词： field programmable gate arrays (FPGA)

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