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检索条件"任意字段=Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis 20

Flexible Communication Avoiding Matrix Multiplication on FPG...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Licht, Johannes de Fine Kwasniewski, Grzegorz Hoefler, Torsten Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781450370998

Data movement is the dominating factor affecting performance and energy in modern computing systems. Consequently, many algorithms have been developed to minimize the number of I/O operations for common computing patterns. Matrix multiplication is no exception, and lower bounds have been proven and implemented both for shared and distributed memory systems. Reconfigurable hardware platforms are a lucrative target for I/O minimizing algorithms, as they offer full control of memory accesses to the programmer. While bounds developed in the context of fixed architectures still apply to these platforms, the spatially distributed nature of their computational and memory resources requires a decentralized approach to optimize algorithms for maximum hardware utilization. We present a model to optimize matrix multiplication for FPGA platforms, simultaneously targeting maximum performance and minimum off-chip data movement, within constraints set by the hardware. We map the model to a concrete architecture using a high-level synthesis tool, maintaining a high level of abstraction, allowing us to support arbitrary data types, and enables maintainability and portability across FPGA devices. Kernels generated from our architecture are shown to offer competitive performance in practice, scaling with both compute and memory resources. We offer our design as an open source project(1) to encourage the open development of linear algebra and I/O minimizing algorithms on reconfigurable hardware platforms.

关键词： i/o optimization linear algebra communication avoiding algorithms matrix multiplication systolic arrays fpga gemm vivado hls high-level synthesis hls

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Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal FPGA Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC FPGA Architecture FPGA CAD Xilinx

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Extending High-Level Synthesis for Task-Parallel Programs 21

Extending High-Level Synthesis for Task-Parallel Programs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Yuze Chi Licheng Guo Young-kyu Choi Jie Wang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450382182

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA *** this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

关键词： high-level synthesis task-parallel program field-programmable gate array

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Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) 19

Versal: The Xilinx Adaptive Compute Acceleration Platform (A...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Vissers, Kees Xilinx 2100 All Programmable Dr San Jose CA 95124 USA

ISBN: (纸本)9781450361378

In this presentation I will present the new Adaptive Compute Acceleration Platform. I will show the overall system architecture of the family of devices including the Arm cores (scalar engines), the programmable logic (Adaptable Engines) and the new vector processor cores (AI engines). I will focus on the new AI engines in more detail and show the architecture, the integration in the total device, the programming environment and some applications, including Machine Learning and 5G wireless applications.

关键词： Versal AI engine VLIW processor

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The P4→NetFPGA Workflow for Line-Rate Packet Processing 19

The P4→NetFPGA Workflow for Line-Rate Packet Processing

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Ibanez, Stephen Brebner, Gordon McKeown, Nick Zilberman, Noa Stanford Univ Stanford CA 94305 USA Xilinx Labs San Jose CA USA Univ Cambridge Cambridge England

ISBN: (纸本)9781450361378

P4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. The goal of the work presented here is to make it easier for engineers, researchers and students to learn how to program using P4, and to build prototypes running on real hardware. Our target is the NetFPGA SUME platform, a 4 x 10 Gb/s PCIe card designed for use in universities for teaching and research. Until now, NetFPGA users have needed to learn an HDL such as Verilog or VHDL, making it off limits to many software developers and students. Therefore, we developed the P4 -> NetFPGA workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the NetFPGA SUME board. The P4 -> NetFPGA workflow is built upon the Xilinx P4-SDNet compiler and the NetFPGA SUME open source code base. In this paper, we provide an overview of the P4 programming language and describe the P4 -> NetFPGA workflow. We also describe how the workflow is being used by the P4 community to build research prototypes, and to teach how network systems are built by providing students with hands-on experience working with real hardware.

关键词： programmable data-planes fpga p4

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An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops 20

An Algorithm for Delay Optimal Logic Replication for FPGAs A...

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proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Rupesh S. Shelar Synopsys Inc. Hillsboro OR USA

ISBN: (纸本)9781450370998

Logic replication is often necessary to improve speed of emulation for systems employing field programmable gate arrays (FPGAs), since design sizes are large enough requiring partitioning to fit a design into multiple (boards of) FPGAs. In this paper, we propose a polynomial time algorithm for combinational logic replication that ensures delay optimality for directed acyclic graphs and reduces overhead due to look-up table (LUT) and cut resources. The algorithm is further extended to consider combinational loops, often yielding delay optimal results. Experimental results on industrial designs show, on an average, 44%, 33%, and 33% reduction in overhead due to cut, LUT costs, and runtimes, respectively, compared to existing heuristics, thus demonstrating the efficiency of the algorithm.

关键词： dynamic programming optimization prototyping field programmable gate arrays (fpgas) timing combinational loops logic replication emulation algorithm

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Classifying Computations on Multi-Tenant FPGAs 21

Classifying Computations on Multi-Tenant FPGAs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Mustafa Gobulukoglu Colin Drewes Bill Hunter Dustin Richmond Ryan Kastner University of California San Diego San Diego CA USA Georgia Tech Research Institute Atlanta GA USA University of Washington Seattle WA USA

ISBN: (纸本)9781450382182

Modern data centers leverage large FPGAs to provide low latency, high throughput, and low energy computation. FPGA multi-tenancy is an attractive option to maximize utilization, yet it opens the door to unique security threats. In this work, we develop a remote classification pipeline that targets the confidentiality of multi-tenant cloud FPGA environments. We design a unique Dual-Edged voltage fluctuation sensor that measures subtle changes in the power distribution network caused by co-located computations. The sensor measurements are given to a classification pipeline that is able to deduce information about co-located applications including the type of computation and its implementation. We study the importance of the trace length, signal conditioning algorithms, and other aspects that affect classification accuracy. Our results show that we can determine if another co-tenant is present with 96% accuracy. We can classify with 98% accuracy whether a power waster circuit is operating. Furthermore, we are able to determine if a cryptographic operation is occurring, differentiate between different cryptographic algorithms (AES and PRESENT) and microarchitectural implementations (Microblaze, ORCA, and PicoRV32).

关键词： programmable logic sensor hardware security power distribution network side-channel analysis neural network multi-tenant FPGA

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A Multiplication-Free FPGA Implementation of Multiple RLWE Encryption using Anti-Circulant Matrix 16

A Multiplication-Free FPGA Implementation of Multiple RLWE E...

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16th IEEE international Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Yang, Chen Zhang, Fahong Wang, Jianfei Su, Yang Xi'an Jiaotong University School of Microelectronics Shaanxi Xi'an710049 China Engineering University of Pap School of Cryptography Engineering Shaanxi Xi'an710086 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

With the expansion of cloud services and privacy security becomes more crucial, fully homomorphic encryption (FHE) scheme which operates data in ciphertext domain has been widely concerned. Lattice-based cryptography ring learning with errors (RLWE), together with its variants RLWE' and RGSW, form the core component of main-stream homomorphic encryption schemes. This paper presents a universal RLWE encryption module supports ciphertext generation of three cryptographic schemes above. The design uses anti-circulant matrix to convert polynomial multiplication to N-level inner product between vector and anti-circulant matrix to wipe off additional modular reduction. Meanwhile, Montgomery reduction is used to realize multiplicationfree polynomial multiplication. The results show that the utilizations of LUT and FF are reduced by 51% and 30% respectively, as well as completely avoiding DSP usage. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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MLBlocks: FPGA Blocks for Machine Learning Applications 21

MLBlocks: FPGA Blocks for Machine Learning Applications

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Seyedramin Rasoulinezhad David Boland Philip H.W. Leong The University of Sydney Sydney Australia

ISBN: (纸本)9781450382182

The underlying goal of FPGA architecture research is to devise flexible substrates which implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing and image processing applications through high precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: 1) higher computational density and 2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) layers. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new compute units, called MLBlocks. These blocks are flexible mesh-based systolic array units parameterized with different data movements, data reuse, and multi-precision support. They utilize a columnar arrangement which is compatible with existing FPGA architectures. Finally, using synthetic benchmarks, we demonstrate that MLBlocks offer significantly improved performance over the commercial Xilinx DSP48E2, while maintaining similar area and timing requirements to current DSPs.

关键词： FPGA architectures reconfigurable architecture neural networks digital signal processing systolic arrays coarse-grained compute blocks

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FPGA 2015 - 2015 acm/sigda international symposium on field-programmable gate arrays

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

ISBN: (纸本)9781450333153

The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point FPGAs;software-driven hardware development;InTime: a machine learning approach for efficient selection of FPGA CAD tool parameters;enhancing hardware design flows with MyHDL;rapid prototyping of wireless physical layer modules using flexible software/hardware design flow;application of specific delay window routing for timing optimization in FPGA designs;application of specific delay window routing for timing optimization in FPGA designs;fine-grained interconnect synthesis;delay-bounded routing for shadow registers;EURECA: on-chip configuration generation for effective dynamic data access;energy-efficient discrete signal processing with field programmable analog arrays (FPAAs);expanding OpenFlow capabilities with virtualized reconfigurable hardware.

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