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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是111-120 订阅

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Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial programmable Architectures 17

Learning Convolutional Neural Networks for Data-Flow Graph M...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Yin, Shouyi Liu, Dajiang Sun, Lifeng Lin, Xinhan Liu, Leibo Wei, Shaojun Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450343541

Data flow graph (DFG) mapping is critical for the compiling of spatial programmable architecture, where compilation time is a key factor for both time-to-market requirement and mapping successful rate. Inspired from the great progress made in tree search game using deep neural network, we proposed a framework for learning convolutional neural networks for mapping DFGs onto spatial programmable architectures. Considering that mapping is a process from source to target, we present a dual-input neural network capturing features from both DFGs in applications and Process Element Array (PEA) in spatial programmable architectures. In order to train the neural network, algorithms are designed to automatically generate a data set from PEA intermediate states of preprocessed DFG. Finally, we demonstrate that the trained neural network can get high identifying accuracy of mapping quality and our proposed mapping approach are competitive with state-of-the-art DFG mapping algorithms in performance while the compilation time is greatly reduced.

关键词： DFG reconfigurable architecture mapping convolutional neural network

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Hardware Scheme for Autonomous Docking Algorithm using FPGA based Mobile Robot 8

Hardware Scheme for Autonomous Docking Algorithm using FPGA ...

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8th IEEE international symposium on Embedded Computing and System Design, ISED 2018

作者： Vani, G. Divya Chinnaiah, M. Karumuri, Srinivasa Rao Department of ECE K L University GunturAndhra Pradesh India Department of ECE B v Raju Institute of Technology Narsapur MedakTelangana India

ISBN: (纸本)9781538665756

This paper proposes the self docking navigation algorithm for autonomous transportation of heavy loads using multiple mobile robots. The proposed method gives novelty in implementation of algorithm using VLSI architectures. All individual nonholonomic robots accompanying themselves with autonomous behaviour control mechanism, are capable in self formation at docking point without any collision. The robots consider indoor environment floor direction in 2D plane (X, X1 and Z, Z1). The hardware schemes are coded in Verilog and same is simulated, synthesized and implemented on FPGA using Xilinx VIVADO tools. FPGAs (Xilinx Zynq-7000 SoC ZC702) are acting as main control unit of the mobile robot prototypes. The FPGA based mobile robots are used for validation of autonomous docking algorithm. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors 17

Measuring the Power-Constrained Performance and Energy Gap b...

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acm/sigda international symposium on field-programmable gate arrays

作者： Ye, Andy Gean Ganesan, Karthik Ryerson Univ Toronto ON Canada Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450343541

This work measures the performance and power consumption gap between the current generation of low power FPGAs and low power microprocessors (microcontrollers) through an implementation of the Canny edge detection algorithm. In particular, the algorithm is implemented on Altera MAX 10 FPGAs and its performance and power consumption are then compared to the same algorithm implemented on the STMicroelectronics' implementation of the ARM M-series microcontrollers. We found an extremely high, four- to five-orders of magnitude, performance advantage of the FPGAs over the microcontrollers, which is much greater than any previously reported values in FPGAs vs. processors studies. Furthermore, this speedup only comes at a cost of 1.2x to 15x higher power consumption, which gives FPGAs a significant advantage in energy efficiency. We also observe, however, the current generation of low power FPGAs have significantly higher static power consumption than the microcontrollers. In particular, the low power FPGAs consume more static power than the total power consumption of the lowest power consuming microcontrollers, rendering the FPGAs inoperable under the power budgets of these processors. Furthermore, this high static power consumption exists despite the fact that the FPGAs are implemented on a low leakage 55nm process with dual supply voltages while the microcontrollers are implemented on a conventional, single supply voltage, 90nm process. Consequently, our results indicate that it is particular important for future research to address the static power consumption of low power FPGAs while maintaining logic capacity so the performance and energy efficiency advantages of the FPGAs can be fully utilized in the extremely low power application domain that are driven by batteries with very small form factors and emerging small scale energy harvesting technologies.

关键词： field programmable gate arrays (FPGAs) Low-Power FPGAs FPGA vs. Microcontroller Performance Energy Efficiency

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Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? 17

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neu...

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acm/sigda international symposium on field-programmable gate arrays

作者： Nurvitadhi, Eriko Venkatesh, Ganesh Sim, Jaewoong Marr, Debbie Huang, Randy Ong, Jason Gee Hock Liew, Yeong Tat Srivatsan, Krishnan Moss, Duncan Subhaschandra, Suchit Boudoukh, Guy Intel Corp Accelerator Architecture Lab Santa Clara CA 95051 USA Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Intel Corp FPGA Prod Team Santa Clara CA 95051 USA Intel Corp Comp Vis Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781450343541

Current-generation Deep Neural Networks (DNNs), such as AlexNet and VGG, rely heavily on dense floating-point matrix multiplication (GEMM), which maps well to GPUs (regular parallelism, high TFLOP/s). Because of this, GPUs are widely used for accelerating DNNs. Current FPGAs offer superior energy efficiency (Ops/Watt), but they do not offer the performance of today's GPUs on DNNs. In this paper, we look at upcoming FPGA technology advances, the rapid pace of innovation in DNN algorithms, and consider whether future high-performance FPGAs will outperform GPUs for next-generation DNNs. The upcoming Intel (R) 14-nm Stratix (TM) 10 FPGAs will have thousands of hard floating-point units (DSPs) and on-chip RAMs (M20K memory blocks). They will also have high bandwidth memories (HBMs) and improved frequency (HyperFlex (TM) core architecture). This combination of features brings FPGA raw floating point performance within striking distance of GPUs. Meanwhile, DNNs are quickly evolving. For example, recent innovations that exploit sparsity (e.g., pruning) and compact data types (e.g., 1-2 bit) result in major leaps in algorithmic efficiency. However, these innovations introduce irregular parallelism on custom data types, which are difficult for GPUs to handle but would be a great fit for FPGA's extreme customizability. This paper evaluates a selection of emerging DNN algorithms on two generations of Intel FPGAs (Arria (TM) 10, Stratix (TM) 10) against the latest highest performance Titan X Pascal GPU. We created a customizable DNN accelerator template for FPGAs and used it in our evaluations. First, we study various GEMM operations for next-generation DNNs. Our results show that Stratix 10 FPGA is 10%, 50%, and 5.4x better in performance (TOP/sec) than Titan X Pascal GPU on GEMM operations for pruned, Int6, and binarized DNNs, respectively. Then, we present a detailed case study on accelerating Ternary ResNet which relies on sparse GEMM on 2-bit weights (i.e., weights constrai

关键词： Deep Learning Accelerator Intel Stratix 10 FPGA GPU

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A Low-power APUF-based Environmental Abnormality Detection Framework 22

A Low-power APUF-based Environmental Abnormality Detection F...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Gu, Hongxiang Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Comp Sci Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781509060238

Physical unclonable functions (PUFs) take advantage of the effect of process variation on hardware to obtain their unclonability. Traditional PUF design only focuses on the analog signals of circuits. An arbiter PUF, for example, generates responses by racing delay signals. Implementations of such PUFs usually employ large area and power consumption while providing very low throughput. To address this problem, we propose an energy efficient PUF design in such a way that it races analog signals and computes digital logic simultaneously. More importantly, the analog portion of the circuit (racing) shares a large amount of hardware resources with the digital portion of the circuit (computing) by introducing only small overhead in terms of area and power. Our test results on Spartan-6 field-programmable gate array (FPGA) platforms indicate that by combining the two outputs, our design enables much larger PUF output throughput, better randomness and less power consumption compared to traditional PUFs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Invited Paper: Ultra-low Energy Security Circuit Primitives for IoT Platforms 22

Invited Paper: Ultra-low Energy Security Circuit Primitives ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mathew, Sanu Satpathy, Sudhir Suresh, Vikram Krishnamurthy, Ram Intel Corp Circuits Res Lab Hillsboro OR 97124 USA

ISBN: (纸本)9781509060238

Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve > 0.99 min-entropy with 3pJ/bit energy-efficiency.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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CORAL: Coarse-grained Reconfigurable Architecture for ConvoLutional Neural Networks 22

CORAL: Coarse-grained Reconfigurable Architecture for ConvoL...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Yuan, Zhe Liu, Yongpan Yue, Jinshan Li, Jinyang Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781509060238

Convolutional Neural Network (CNN) has become one of the most successful technologies for visual classification and other applications. As CNN models continue to evolve and adopt different kernel sizes in various applications, it is necessary for the hardware architecture to support reconfigurability. Previous FPGAs and programmable ASICs are fine-grained reconfigurable but with energy efficiency compromise. Considering specific features of CNNs, this paper presents an energy efficient coarse-grained reconfigurable architecture, denoted as CORAL. An application-specific configuration neural block is proposed for convolution operations with reconfigurable data quantization to reduce both energy consumption and on-chip memory requirements. An optimal data loading strategy is presented for CORAL to achieve the best energy efficiency. Experimental results show that CORAL improves 80.0% energy efficiency while reduces 78.9% chip area and 81.0% reconfiguration time compared with the best up-to-date programmable ASIC solution.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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ASAP: Accelerated Short Read Alignment on programmable Hardware 17

ASAP: Accelerated Short Read Alignment on Programmable Hardw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Banerjee, Subho S. el-Hadedy, Mohamed Lim, Jong B. Chen, Daniel Kalbarczyk, Zbigniew T. Chen, Deming Iyer, Ravishankar K. Univ Illinois Champaign IL USA

ISBN: (纸本)9781450343541

The proliferation of high-throughput sequencing machines allows for the rapid generation of billions of short nucleotide fragments in a short period. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This poster explores the use of hardware acceleration to significantly improve the runtime of short-read alignment (SRA), a crucial step in pre-processing sequenced genomes. It presents the design and implementation of ASAP, an accelerator for computing Levenshtein distance (LD) in the context of the SRA problem. LD computation is a prominent underlying mathematical kernel that is common to a large number of SRA tools (e.g., BLAST, BWA, SNAP) and is responsible for 50-70% of their runtime. These algorithms mentioned above calculate the exact value of LD between nucleotide strings but only use them to build a total ordering (an ordered list) of the most likely point of origin in the genome. ASAP computes an approximation of LD by encoding computation in propagation delay of circuit elements. This approximation is calculated in an accelerated fashion in hardware and preserves the original total ordering of LDs produced by the traditional algorithms. This computation is performed by constructing circuits that comprise the recursive definition of the LD computation and measuring propagation delay of a signal entering and leaving the circuit. Additionally, ASAP can explore large portions of the search space (substrings of the strings being compared) within one clock cycle, and ignore parts of the search space that does not contribute to an answer. Our design is implemented on an Altera Stratix V FPGA in an IBM POWER8 system using the CAPI interface for cache coherence across the CPU and FPGA. Our design is 200x faster (median measurement) than the equivalent C implementation of the kernel running on the host processor and 2.2x faster for an end-to-end alignment tool for 120-150bp short-read sequences.

关键词： FPGA Bioinformatics Genomics

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Battery Assignment and Scheduling for Drone Delivery Businesses 22

Battery Assignment and Scheduling for Drone Delivery Busines...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Park, Sangyoung Zhang, Licong Chakraborty, Samarjit Tech Univ Munich Chair Real Time Comp Syst Munich Germany

ISBN: (纸本)9781509060238

Recent advances in battery and drone technologies have opened up possibilities of commercial use of drones. Private companies are looking into the possibilities of using drones for commercial deliveries from the legal, technical, and economical perspective. Nevertheless, the battery management perspective of such businesses has not yet been thoroughly investigated. In this paper, we identify that battery management of such application has a major impact of the costs, and formulate an optimization problem to reduce the aging of batteries. We identify two subproblems, battery assignment, and battery scheduling to derive a solution that minimizes the aging of the batteries. We show that the formulation enables leveraging the trade-off relationships between the packet waiting time and battery purchasing cost. The experimental results show the proposed method reduce the electricity and battery purchasing cost by 25%, and average packet waiting time by more than 50%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology 22

Low Design Overhead Timing Error Correction Scheme for Elast...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ryu, Sungju Koo, Jongeun Kim, Jae-Joon Pohang Univ Sci & Technol Pohang South Korea

ISBN: (纸本)9781509060238

The elastic clock scheme is a robust design methodology to ensure timing closure under PVT variation using locally generated clocks and handshaking protocol. However, it still has a chance of timing errors due to delay mismatch between the data-path and delay replica. In this paper, we propose a low design overhead timing error correction scheme tailored to elastic clock. In the proposed scheme, a timing error can be corrected within a cycle using clock stretching. The proposed scheme shows 40.3X and 4.6X reduction in timing margin with 9.1% and 9.0% area overhead over the synchronous baseline and elastic clock design, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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