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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是121-130 订阅

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Hotspot Monitoring and Temperature Estimation with Miniature On-Chip Temperature Sensors 22

Hotspot Monitoring and Temperature Estimation with Miniature...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chundi, Pavan Kumar Zhou, Yini Kim, Martha Kursun, Eren Seok, Mingoo Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781509060238

This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Improved Clocking Methodology for Energy Efficient Low Area AES Architectures using Register Renaming 22

An Improved Clocking Methodology for Energy Efficient Low Ar...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Dhanuskodi, Siva Nishok Holcomb, Daniel Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781509060238

Sub-round implementations of AES have been explored as an area and energy efficient solution to encrypt data in resource constrained applications such as the Internet of Things. Symmetry in AES operations across bytes and words allows the datapath to be scaled down to 8 bits resulting in very compact designs. However, such designs incur an area penalty to store intermediate results or energy penalty to shift data through registers without performing useful computation. We propose a smart clocking scheme and rename registers to minimize data movement and clock loading, and also avoid storing a duplicate copy of the system state. In comparison to the most efficient 8-bit implementation from literature, we save 45% energy per encryption and reduce clock energy by 70% at a reasonable area cost.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O 22

Enabling Efficient Fine-Grained DRAM Activations with Interl...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Zhang, Chao Guo, Xiaochen Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA

ISBN: (纸本)9781509060238

DRAM contributes a significant part of the total system energy consumption, and row activation is one of the most energy inefficient components. Prior works on fine-grained DRAM activation rely on increasing the number of local wires to avoid degrading performance, which adds area overheads. This work proposes interleaved I/O to allow data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture allows half-, quarter-, or one-eighth-page activations without changing the wires. The system performance is competitive as compared with other finegrained activation designs. For the evaluated benchmarks, an average of up to 15.7% performance improvement is achieved among all of the configurations. Furthermore, the total DRAM energy can be reduced by an average of 11.2% for halfpage, 17.2% for quarterpage, and 22.3% for one-eighth-page.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Efficient Thermoelectric Cooling for Mobile Devices 22

Efficient Thermoelectric Cooling for Mobile Devices

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Lee, Youngmoon Kim, Eugene Shin, Kang G. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509060238

Mobile apps suffer large performance degradation when the underlying processors are throttled to cool down the devices. Fans or heat sinks are not a viable option for mobile devices, thus calling for a new portable cooling solution. Thermoelectric coolers are scalable and controllable cooling devices that can be embedded into mobile devices on the chip surface. This paper presents a thermoelectric cooling solution that enables efficient processor thermal management in mobile devices. Our goal is to minimize performance loss from thermal throttling by efficiently using thermoelectric cooling. Since mobile devices experience large variations in workloads and ambient temperature, our solution adaptively controls cooling power at runtime. Our evaluation on a smartphone using mobile benchmarks demonstrated that the performance loss from the maximum speed is only 1.8% with the TEC compared to 19.2% without the TEC.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Prototyping dynamic task migration on heterogeneous reconfigurable systems 28

Prototyping dynamic task migration on heterogeneous reconfig...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Sasongko, Arif Rousseau, Frédéric Univ. Grenoble Alpes TIMA CNRS Grenoble France Institut Teknologi Bandung Bandung Indonesia

ISBN: (纸本)9781450354189

Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented. © 2017 acm.

关键词： field programmable gate arrays (FPGA)

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Workload-Driven Frequency-Aware Battery Sizing 22

Workload-Driven Frequency-Aware Battery Sizing

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chen, Yukai Macii, Enrico Poncino, Massimo Politecn Torino Dept Control & Comp Engn Turin Italy

ISBN: (纸本)9781509060238

Despite the wide body of literature on the sizing of energy storage devices available in the domain of electrical energy systems, the problem has not drawn much attention in the area of battery-powered electronic systems. It is well-known that the straightforward method of sizing battery as the product of an expected duration and the average load current always underestimates the actual capacity that the battery can supply. The variability of the workload and of its spectral distribution will in fact affect the effective capacity of battery that cannot be ignored. This paper proposed a methodology to compute the required capacity of a battery based on the properties of the workload;in particular it accounts for both the impact of the distribution of the current load and of its frequencies, and determines corrective factors for both effects to be used for the calculation of the actual capacity. We used a frequency-sensitive circuit-equivalent battery model to validates our method on three synthetic and two real workloads. Simulation results show that even for workload with same average current, the required capacity can be as much as 70% larger than the capacity estimated using a traditional method.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Simple Yet Efficient Accuracy Configurable Adder Design 22

A Simple Yet Efficient Accuracy Configurable Adder Design

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Xu, Wenbin Sapatnekar, Sachin S. Hu, Jiang Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)9781509060238

Approximate computing is a promising approach for low power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy configurable adder designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of these designs include error detection and correction circuitry, which further increases area. In this work, we investigate a simple accuracy configurable adder design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. Simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% lower area. Moreover, we propose a delay-adaptive self-configuration technique to further improve accuracy-delay-power tradeoff.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Simulation-based circuit-activity estimation for FPGAs containing hard blocks 28

Simulation-based circuit-activity estimation for FPGAs conta...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Seeley, Sean Sankaranaryanan, Vidya Deveau, Zack Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick Canada

ISBN: (纸本)9781450354189

FPGAs are electronic devices that are programmable and can functionally perform equivalently to a number of other circuits. FPGAs are used for both rapid and cheap prototyping of new circuit designs as well as for replacing outdated chip models. Due to their complexity, circuits cannot be practically designed by hand;instead, specialized Computer Aided Design (CAD) software performs this complex task. A major concern for devices is power requirements, which can have adverse effects on both the environment and users. The power requirements of a circuit can be directly connected with its activity, which can be estimated by the CAD tools. In this work, we focus on the open source Verilog-To-Routing (VTR) CAD software and propose an improved activity estimation tool using VTR's synthesizer (Odin II) that extends beyond the capabilities of its current estimator (ACE2), such as proper black box activity propagation and support for circuits containing no clocks or more than one clock. Our results are experimentally evaluated with VTR's FPGA architectures and benchmark circuits. © 2017 acm.

关键词： field programmable gate arrays (FPGA)

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XNOR-POP: A Processing-in-Memory Architecture for Binary Convolutional Neural Networks in Wide-I02 DRAMs 22

XNOR-POP: A Processing-in-Memory Architecture for Binary Con...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Jiang, Lei Kim, Minje Wen, Wujie Wang, Danghui Indiana Univ Bloomington Bloomington IN 47405 USA Florida Int Univ Miami FL 33199 USA Northwestern Polytech Univ Fremont CA USA

ISBN: (纸本)9781509060238

It is challenging to adopt computing-intensive and parameter-rieh Convolutional Neural Networks (CNNs) in mobile deviees due to limited hardware resources and low power budgets. To support multiple concurrently running applications, one mobile deviee needs to perform multiple CNN tests simultaneously in real-time. Previous solutions cannot guarantee a high enough frame rate when serving multiple applications with reasonable hardware and power cost. In this paper, we present a novel process-in-memory architecture to process emerging binary CNN tests in Wide-I02 DRAMs. Compared to state-of-the-art accelerators, our design improves CNN test performance by 4x rv llx with small hardware and power overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Placement Mitigation Techniques for Power Grid Electromigration 22

Placement Mitigation Techniques for Power Grid Electromigrat...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ye, Wei Lin, Yibo Xu, Xiaoqing Li, Wuxi Fu, Yiwei Sun, Yongsheng Zhan, Canhui Pan, David Z. Univ Texas Austin ECE Dept Austin TX 78712 USA Hisilicon Technol Co Ltd Shenzhen Peoples R China

ISBN: (纸本)9781509060238

In advanced technology nodes, power grid metal wires are prone to electromigration (EM) failures due to small wire sizes and high unidirectional current densities. Power grid EM failures usually happen around weak power grid connections delivering current to high power-consuming regions. Previously, power grid EM was mostly addressed at the post-routing stage, which may be too late for a large number of EM violations in modern designs. In this paper, we propose a new set of incremental placement techniques to mitigate power grid EM, including cell move, single row placement, and single tile placement. Experimental results demonstrate the proposed placement techniques can effectively reduce EM violations with negligible wirelength and placement density impacts.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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