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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是131-140 订阅

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Experimental Validation of the Performance Improvement Obtained by Using Two Similar Passive Bistatic Radar Systems 18

Experimental Validation of the Performance Improvement Obtai...

引用

18th international Radar symposium (IRS)

作者： Baruzzi, Aurora Heckenbach, Joerg Cristallini, Diego Schwark, Christoph Finden, Erlend Norheim-Naess, Idar Strom, Kyrre Fraunhofer Inst Hochfrequenzphys & Radartech Fraunhoferstr 20 D-53343 Wachtberg Germany Norwegian Def Res Estab FFI POB 25 NO-2027 Kjeller Norway

This paper tests and demonstrates the ability of a twin set of passive radar systems to monitor real time an area of interest and track medium size targets. The results are based on a real data acquisition campaign pe... 详细信息

ISBN: (纸本)9783736993433

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Learning Bridge from Architectural Synthesis to Physical Design for Exploring Power Efficient High-Performance Adders 22

A Learning Bridge from Architectural Synthesis to Physical D...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Roy, Subhendu Ma, Yuzhe Miao, Jin Yu, Bei Cadence Design Syst San Jose CA 95134 USA Chinese Univ Hong Kong CSE Dept Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781509060238

In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become suboptimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a stateof- the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Experimental results demonstrate that our framework can achieve near-optimal delay vs. power/ area Pareto frontier over a wide design space, bridging the gap between architectural and physical designs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Case for Efficient Accelerator Design Space Exploration via Bayesian Optimization 22

A Case for Efficient Accelerator Design Space Exploration vi...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Reagen, Brandon Hernandez-Lobato, Jose Miguel Adolf, Robert Gelbart, Michael Whatmough, Paul Wei, Gu-Yeon Brooks, David Harvard Univ Cambridge MA 02138 USA Univ Cambridge Cambridge England Univ British Columbia Vancouver BC Canada ARM Res Cambridge England

ISBN: (纸本)9781509060238

In this paper we propose using machine learning to improve the design of deep neural network hardware accelerators. We show how to adapt multi-objective Bayesian optimization to overcome a challenging design problem: optimizing deep neural network hardware accelerators for both accuracy and energy efficiency. DNN accelerators exhibit all aspects of a challenging optimization space: the landscape is rough, evaluating designs is expensive, the objectives compete with each other, and both design spaces (algorithmic and microarchitectural) are unwieldy. With multi-objective Bayesian optimization, the design space exploration is made tractable and the design points found vastly outperform traditional methods across all metrics of interest.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Tiguan: Energy-Aware Collision-Free Control for Large-Scale Connected Vehicles 22

Tiguan: Energy-Aware Collision-Free Control for Large-Scale ...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Shen, Minghua Luo, Guojie Peking Univ Ctr Energy Efficient Comp & Applicat Sch EECS Beijing Peoples R China NUDT Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China

ISBN: (纸本)9781509060238

Traditional transportation systems in metropolitan areas always suffer from energy inefficiencies, evidenced by its uncoordinated behaviors such as system capacity and traffic demand change. With the advanced networked sensors are prevalent deployed into the autonomous vehicles, the information of system status and traffic demand can be collected in real-time. These information provides the potential to perform different types of coordination and control for autonomous vehicles in large-scale intelligent transportation systems. In this paper, we design a coordination-based energy-aware control method for large-scale connected vehicles, named Tiguan. Tiguan enables an iterative scheme to compute a practicable solution, which all vehicles are controlled on different trajectory paths of ground traffic network while achieving the close to the optimal performance. Safety is guaranteed by enabling vehicle to autonomously coordinate with other vehicles for a road traffic resource, and thus determine which vehicle needs the resource most. Experimental results show that Tiguan can effectively generate a feasible control solution with collision avoidance, and minimizing the energy consumption.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs 22

Frequency and Time Domain Analysis of Power Delivery Network...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Das, Shidhartha Sinha, Saurabh Cline, Brian Yeric, Greg Lim, Sung Kyu Georgia Inst Teehnol Sch ECE Atlanta GA 30332 USA ARM Ltd Cambridge England ARM Inc Austin TX USA

ISBN: (纸本)9781509060238

As 2D scaling reaches its limit, monolithic 3D IC (M3D) is a leading contender to continue equivalent scaling. AIthough M3D shows power and performance benefits over 2D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power-supply integrity. In addition, we present frequency- and time-domain analysis of the M3D PDN. We show that the additional resistance in the M3D PDN, while being worse for resistive drops, improves resiliency against current noise showing 35.9% peak impedance reduction during worst-case resonant oscillations.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Temporal Codes in On-Chip Interconnects 22

Temporal Codes in On-Chip Interconnects

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mishkin, Michael Kim, Nam Sung Lipasti, Mikko Univ Wisconsin Madison Madison WI USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781509060238

Dynamic power consumption associated with signal toggles over long distance wires accounts for a significant portion of onchip interconnect power. Improving dynamic energy efficiency in highly capacitive interconnects can be achieved by reducing the toggle rates associated with data communication. Temporal coding schemes facilitate bounded activity factors by encoding information as placement of signal toggles in time and can thereby improve the energy efficiency of data communication by encoding multiple bits per toggle. We introduce two temporal protocol variants designed for traversal of the crossbars in on-chip networks. These protocols reduce peak power without loss of bandwidth and achieve energy efficient onchip communication in high capacitance long distance interconnects. Extending these energy savings to a multi-hop mesh topology is achieved by router implementations equipped with bypassing mechanisms that elide per hop reencoding overheads. We demonstrate a four bit per transition temporal protocol with up to 75% communication energy reduction that can be achieved over a baseline serial bit stream protocol.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Full Chip Power Benefits with Negative Capacitance FETs 22

Full Chip Power Benefits with Negative Capacitance FETs

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Samal, Sandeep K. Khandelwal, Sourabh Khan, Asif I. Salahuddin, Sayeef Hu, Chenming Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Macquarie Univ Dept Engn Sydney NSW Australia Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)9781509060238

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercialgrade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4X (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Efficient Query Processing in Crossbar Memory 22

Efficient Query Processing in Crossbar Memory

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Imani, Mohsen Gupta, Saransh Arredondo, Atl Rosing, Tajana Univ Calif San Diego CSE Dept La Jolla CA 92093 USA

ISBN: (纸本)9781509060238

Today's computing systems use huge amount of energy and time to process basic queries in database. A large part of it is spent in data movement between the memory and processing cores, owing to the limited cache capacity and memory bandwidth of traditional computers. In this paper, we propose a non-volatile memory-based query accelerator, called NVQuery, which performs several basic query functions in memory including aggregation, prediction, bit-wise operations, as well as exact and nearest distance search queries. NVQuery is implemented on a content addressable memory (CAM) and exploits the analog characteristic of non-volatile memory in order to enable in-memory processing. To implement nearest distance search in memory, we introduce a novel bitline driving scheme to give weights to the indices of the bits during the search operation. Our experimental evaluation shows that, NVQuery can provide 49.3x performance speedup and 32.9x energy savings as compared to running the same query on traditional processor. In addition, compared to the state-of-the-art query accelerators, NVQuery can achieve 26.2x energy-delay product improvement while providing the similar accuracy.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Exploring Sparsity of Firing Activities and Clock Gating for Energy-Efficient Recurrent Spiking Neural Processors 22

Exploring Sparsity of Firing Activities and Clock Gating for...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Liu, Yu Jin, Yingyezhe Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781509060238

As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its FPGA implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed FPGA-based neural processor system is up to 2 9 % more energy efficient than a baseline LSM processor with little extra hardware overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Energy-efficient and High-throughput Bitwise CNN on Sneak-path-free Digital ReRAM Crossbar 22

An Energy-efficient and High-throughput Bitwise CNN on Sneak...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ni, Leibin Liu, Zichuan Song, Wenhao Yang, J. Joshua Yu, Hao Wang, Kanwen Wang, Yuangang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Huawei Technol Co Ltd Data Ctr Technol Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781509060238

Convolutional neural network (CNN) based machine learning requires a highly parallel as weIl as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM cross bar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of I-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91. 4% accuracy on MNIST and CIFAR-IO benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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