检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

610 篇 会议
32 篇 期刊文献

馆藏范围

642 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

551 篇 工学
- 495 篇 计算机科学与技术...
- 283 篇 软件工程
- 224 篇 电子科学与技术（可...
- 184 篇 电气工程
- 91 篇 信息与通信工程
- 36 篇 控制科学与工程
- 34 篇 动力工程及工程热...
- 24 篇 机械工程
- 15 篇 生物工程
- 12 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 6 篇 测绘科学与技术
- 4 篇 光学工程
- 3 篇 农业工程
199 篇 理学
- 165 篇 数学
- 34 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 8 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 医学

主题

295 篇 field programmab...
172 篇 field programmab...
65 篇 clocks
64 篇 signal processin...
64 篇 estimation
63 篇 modulation
63 篇 ofdm
63 篇 filtration
30 篇 fpga
8 篇 routing
8 篇 optimization
8 篇 field-programmab...
7 篇 fpgas
7 篇 systolic arrays
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...
5 篇 programmable log...
5 篇 logic gates

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
5 篇 intel corporatio...
4 篇 univ british col...
4 篇 tsinghua univers...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 nanyang technol ...
3 篇 computer science...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 nanyang technol ...
3 篇 xilinx inc. san ...
3 篇 politecn milan d...
3 篇 school of comput...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
10 篇 chen deming
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 kiah han mao
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...

语言

635 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是141-150 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

QuARK: Quality-configurable Approximate STT-MRAM Cache by Fine-grained Tuning of Reliability-Energy Knobs 22

QuARK: Quality-configurable Approximate STT-MRAM Cache by Fi...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Monazzah, Amir Mahdi Hosseini Shoushtari, Majid Miremadi, Seyed Ghassem Rahmani, Amir M. Dutt, Nikil Sharif Univ Technol Dept Comp Engn Tehran Iran TU Wien Inst Comp Technol Vienna Austria Univ Calif Irvine Dept Comp Sci Irvine CA USA

ISBN: (纸本)9781509060238

Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/ write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This paper proposes QuARK, a hardware/ software approach for trading reliability of STT-MRAM caches for energy savings in the on-chip memory hierarchy of multi-and many-core systems running approximate applications. In contrast to SRAM-based cache-way-level actuators, QuARK utilizes fine-grained cache-line-level actuation knobs with different levels of reliability for individual read and write accesses which are unique to STT-MRAM and suitable for systems running multiple applications with mixed accuracy sensitivity, thus avoiding interapplication actuation interference. Our experimental results with a set of recognition, mining and synthesis (RMS) benchmarks demonstrate up to 40% energy savings over a fully-protected STT-MRAM cache, with negligible loss in the quality of the generated outputs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Design High Bandwidth-Density, Low Latency and Energy Efficient On-Chip Interconnect 22

Design High Bandwidth-Density, Low Latency and Energy Effici...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Wang, Yong Wu, Hui Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781509060238

For future high-performance computing chips, onchip interconnect requires large bandwidth-density, low latency, and high energy-efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on-chip interconnect. First, we conduct an optimization of on-chip transmission lines to minimize the size, channel loss and inter-symbol-interference (ISI), hence to maximize the bandwidth-density. Based on the result, differential coplanar waveguide (CPW) with 55-mu m pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time-domain pulse responses. Various equalizers are studied, which are used to increase the ISI-limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non-returnto- zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28-nm CMOS technology. An 84-Gb/s PAM-8 transceiver achieves 1.5Gb/ s/mu m bandwidth-density over a 4-cm channel. The unrepeated bandwidth-density is 6.1 Gb/s/mu m-cm, which is almost 10 times larger compared to prior work.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Approximate Memory Compression for Energy-efficiency 22

Approximate Memory Compression for Energy-efficiency

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ranjan, Ashish Raha, Arnab Raghunathan, Vijay Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Memory subsystems are a major energy bottleneck in computing platforms due to frequent transfers between processors and off-chip memory. We propose approximate memory compression, a technique that leverages the intrinsic resilience of emerging workloads such as machine learning and data analytics to reduce off-chip memory traffic and energy. To realize approximate memory compression, we enhance the memory controller to be aware of memory regions that contain approximation-resilient data, and to transparently compress/decompress the data written to/read from these regions. To provide control over approximations, the quality-aware memory controller conforms to a specified error constraint for each approximate memory region. We design a software interface that programmers can use to identify data structures that are resilient to approximations. We also propose a runtime quality control framework that automatically determines the error constraints for the identified data structures such that a given target application-level quality is maintained. We evaluate our proposal by implementing a hardware prototype using the Intel UniPHY-DDR3 memory controller and NIOS-II processor, a Hynix DDR3 DRAM module, and a Stratix-IV FPGA development board. Across a suite of 8 machine learning benchmarks, approximate memory compression obtains a 1.28 x benefit in DRAM energy and a simultaneous 11.5% improvement in execution time for a small (< 1.5%) loss in output quality.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

AXSERBUS: A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensing 22

AXSERBUS: A Quality-Configurable Approximate Serial Bus for ...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Kim, Younghyun Behroozi, Setareh Raghunathan, Vijay Raghunathan, Anand Univ Wisconsin Dept Elect & Comp Engn Maison WI 53706 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Mobile, wearable, and implantable devices integrate an increasing number and variety of sensors such as microphones, image sensors, and accelerometers. These devices spend substantial amounts of time reading the sensors within them, thereby incurring significant energy dissipation over off-chip serial interconnects. This paper proposes AXSERBUS, a quality-configurable approximate serial bus that exploits the locality of sensory data and the error resiliency of sensing applications to reduce energy dissipation. AXSERBUS significantly reduces signal transitions by encoding the differentials of sensory data in three encoding modes, depending on the magnitude of the differentials: very small differentials are zeroed out, incurring no energy dissipation;intermediate differentials are encoded using special low-transition count patterns;and for high differentials, the absolute value (not the differential) of the data is transmitted. Compared to previous schemes, the proposed multi-level encoding results in more data being encoded as low-energy patterns. In addition, in the intermediate differential encoding mode, the differentials are encoded in an approximate manner, and the approximation bounds are proportional to the magnitude of the differentials. Since small differentials are more frequent than large differentials in sensory data, the proposed encoding scheme also minimizes quality degradation. We demonstrate that AXSERBUS achieves improved energy vs. quality tradeoffs compared to previous schemes. In the context of an optical character recognition (OCR) application, AXSERBUS achieves 79.4% reduction in dynamic power dissipation, while maintaining accuracy above 95%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Transistor-Level Monolithic 3D Standard Cell Layout Optimization for Full-Chip Static Power Integrity 22

Transistor-Level Monolithic 3D Standard Cell Layout Optimiza...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ku, Bon Woong Song, Taigon Nieuwoudt, Arthur Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Synopsys Inc Mountain View CA USA

ISBN: (纸本)9781509060238

Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition 22

Monolithic 3D IC Designs for Low-Power Deep Neural Networks ...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Kadetotad, Deepak Cao, Yu Seo, Jae-sun Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Arizona State Univ Sch ECEE Tempe AZ USA

ISBN: (纸本)9781509060238

In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

OLAF′16: Second international Workshop on Overlay Architectures for FPGAs 16

OLAF′16: Second International Workshop on Overlay Architect...

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450338561

The Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: The 24th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.

关键词： FPGA Overlay architecture

来源：评论

学校读者我要写书评

暂无评论

F-SAR - Recent Upgrades and Campaign Activities 18

F-SAR - Recent Upgrades and Campaign Activities

引用

18th international Radar symposium (IRS)

作者： Horn, Ralf Jaeger, Marc Keller, Martin Limbach, Markus Nottensteiner, Anton Pardini, Matteo Reigber, Andreas Scheiber, Rolf German Aerosp Ctr DLR eV Microwaves & Radar Inst Muenchner Str 20 Wessling Germany

ISBN: (纸本)9783736993433

The F-SAR instrument represents DLR's advanced airborne SAR testbed for technology and remote sensing applications. The development of the instrument was triggered by a strong demand for data being simultaneously acquired at different wavelengths and polarizations as well as by the demand for very high range resolution. F-SAR is a modular development utilizing modern hardware and commercial of the shelf components. For the purpose of experiments and operational data acquisition campaigns the system is being installed on board a DLR Dornier DO228 research aircraft. This paper gives an overview of the instrument's capabilities and performance, based on the multi-frequency and fully polarimetric imagery acquired during campaigns in the last two years. More specifically, campaigns in Greenland in 2015 (ARCTIC) and Gabon in 2016 (AfriSAR) are presented.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic 22

A Carbon Nanotube Transistor based RISC-V Processor using Pa...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Amarnath, Aporva Feng, Siying Pal, Subhankar Ajayi, Tutu Rovinski, Austin Dreslinski, Ronald G. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509060238

With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over siliconbased counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energyefficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9. EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5x as well as reduce area by 17% over 16 nm silicon CMOS.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Geometric Orthogonal Codes Better than Optical Orthogonal Codes

Geometric Orthogonal Codes Better than Optical Orthogonal Co...

引用

IEEE international symposium on Information Theory (ISIT)

作者： Chee, Yeow Meng Kiah, Han Mao Ling, San Wei, Hengjia Nanyang Technol Univ Sch Phys & Math Sci Singapore Singapore

ISBN: (纸本)9781509040964

The class of geometric orthogonal codes (GOCs) were introduced by Doty and Winslow (2016) for more robust macrobonding in DNA origami. They observed that GOCs are closely related to optical orthogonal codes (OOCs). It is possible for GOCs to have size greater than OOCs of corresponding parameters due to slightly more relaxed constraints on correlations. However, the existence of GOCs exceeding the size of optimal OOCs of corresponding parameters have never been demonstrated. This paper gives the first infinite family of GOCs of size greater than optimal OOCs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共65页 << < 11 12 13 14 15 16 17 18 19 20 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：