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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是181-190 订阅

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FCUDA-SoC: Platform Integration for field-programmable SoC with the CUDA-to-FPGA Compiler 16

FCUDA-SoC: Platform Integration for Field-Programmable SoC w...

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Nguyen, Tan Gurumani, Swathi Rupnow, Kyle Chen, Deming Adv Digital Sci Ctr Singapore Singapore Univ Illinois Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9781450338561

Throughput oriented high level synthesis allows efficient design and optimization using parallel input languages. Parallel languages offer the benefit of parallelism extraction at multiple levels of granularity, offering effective design space exploration to select efficient single core implementations, and easy scaling of parallelism through multiple core instantiations. However, study of high level synthesis for parallel languages has concentrated on optimization of core and on-chip communications, while neglecting platform integration, which can have a significant impact on achieved performance. In this paper, we create an automated flow to perform efficient platform integration for an existing CUDAto-RTL throughput oriented HLS, and we open source the FCUDA tool, platform integration, and benchmark applications. We demonstrate platform integration of 16 benchmarks on two Zynq-based systems in bare-metal and OS mode. We study implementation optimization for platform integration, compare to an embedded GPU (Tegra TK1) and verify designs on a Zedboard Zynq 7020 (bare-metal) and Omnitek Zynq 7045 (OS).

关键词： System-on-chip

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On the Information Dimension Rate of Stochastic Processes

On the Information Dimension Rate of Stochastic Processes

引用

IEEE international symposium on Information Theory (ISIT)

作者： Geiger, Bernhard C. Koch, Tobias Tech Univ Munich Inst Commun Engn D-80333 Munich Germany Univ Carlos III Madrid Signal Theory & Commun Dept Leganes 28911 Spain Gregorio Maranon Hlth Res Inst Madrid 28007 Spain

ISBN: (纸本)9781509040964

Jalali and Poor ("Universal compressed sensing," arXiv:1406.7807v3, Jan. 2016) have recently proposed a generalization of Renyi's information dimension to stationary stochastic processes by defining the information dimension of the stochastic process as the information dimension of k samples divided by k in the limit as k -> infinity. This paper proposes an alternative definition of information dimension as the entropy rate of the uniformly-quantized stochastic process divided by minus the logarithm of the quantizer step size 1/m in the limit as m -> infinity. It is demonstrated that both definitions are equivalent for stochastic processes that are psi*-mixing, but that they may differ in general. In particular, it is shown that for Gaussian processes with essentially-bounded power spectral density (PSD), the proposed information dimension equals the Lebesgue measure of the PSD's support. This is in stark contrast to the information dimension proposed by Jalali and Poor, which is 1 if the process's PSD is positive on a set of positive Lebesgue measure, irrespective of its support size.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Cooling Codes: Thermal-Management Coding for High-Performance Interconnects

Cooling Codes: Thermal-Management Coding for High-Performanc...

引用

IEEE international symposium on Information Theory (ISIT)

作者： Chee, Yeow Meng Etzion, Tuvi Kiah, Han Mao Vardy, Alexander Nanyang Technol Univ Sch Phys & Math Sci Singapore Singapore Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA

ISBN: (纸本)9781509040964

High temperatures have dramatic negative effects on interconnect performance. Numerous techniques have been proposed to reduce the power dissipation of on-chip buses but they fall short of fully addressing the thermal challenges posed by high-performance interconnects. We introduce new efficient coding schemes that directly control the peak temperature of a bus by effectively cooling its hottest wires. This is achieved by avoiding state transitions on the hottest wires for as long as necessary until their temperature drops off. At the same time, we reduce the average power consumption by ensuring that the total number of state transitions on all the wires is bounded. Our solutions call for redundancy: we use n > k wires to encode a given k-bit bus. Therefore, it is important to determine the minimum possible number of wires n needed to encode k bits while satisfying the desired properties. We provide full analysis in each case, and show that the number of additional wires required to cool the t hottest wires is negligible when k is large. Moreover, the resulting encoders and decoders are fully practical. They do not require significant computational overhead and can be implemented without sacrificing a large circuit area.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Explicit Constructions of Finite-Length WOM Codes

Explicit Constructions of Finite-Length WOM Codes

引用

IEEE international symposium on Information Theory (ISIT)

作者： Chee, Yeow Meng Kiah, Han Mao Vardy, Alexander Yaakobi, Eitan Nanyang Technol Univ Sch Phys & Math Sci Singapore Singapore Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA Technion Israel Inst Technol Dept Comp Sci IL-32000 Haifa Israel

ISBN: (纸本)9781509040964

Write-once memory (WOM) is a storage device consisting of binary cells which can only increase their levels. A t-write WOM code is a coding scheme which allows to write t times to the WOM without decreasing the levels of the cells. The sum-rate of a WOM code is the ratio between the total number of bits written to the memory and the number of cells. It is known that the maximum sum-rate of a t-write WOM code is log(t + 1). This is also an achievable upper bound both by information theory arguments and explicit WOM code constructions. While existing constructions of WOM codes were targeted to increase the sum-rate, we consider here two more figures of merit. in evaluating the constructions. The first one is the complexity of the encoding and decoding maps of the code. The second one is called the convergence rate, and is defined to be the minimum code length n(epsilon) in order to reach epsilon close to a point in the capacity region. One of our main results in the paper is a specific capacity achieving construction for two-write WOM codes which has polynomial complexity and relatively short block length to be c close to the capacity. Using these two-write WOM codes, we obtain three-write WOM codes that approach sum-rate 1.809 with relatively short block lengths. Finally, we provide another construction of three-write WOM that achieves sum-rate 1.71 by using only 100 cells.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Triple-Fault-Tolerant Binary MDS Array Codes with Asymptotically Optimal Repair

Triple-Fault-Tolerant Binary MDS Array Codes with Asymptotic...

引用

IEEE international symposium on Information Theory (ISIT)

作者： Hou, Hanxu Lee, Patrick P. C. Han, Yunghsiang S. Hu, Yuchong Dongguan Univ Technol Sch Elect Engn & Intelligentizat Dongguan Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Hubei Peoples R China

ISBN: (纸本)9781509040964

Binary maximum distance separable (MDS) array codes are a special class of erasure codes for distributed storage that not only provide fault tolerance with minimum storage redundancy, but also achieve low computational complexity. They are constructed by encoding k information columns into r parity columns, in which each element in a column is a bit, such that any k out of the k + r columns suffice to recover all information bits. In addition to providing fault tolerance, it is critical to improve repair performance. Specifically, if a single column fails, our goal is to minimize the repair bandwidth by downloading the least amount of bits from d non-failed columns, where k <= d <= k + r - 1. However, existing binary MDS codes that achieve high data rates (i.e., k/(k + r) > 1/2) and minimum repair bandwidth only support double fault tolerance (i.e., r = 2), which is insufficient for failure-prone distributed storage environments in practice. This paper fills the void by proposing an explicit construction of triple-fault-tolerant (i.e., r = 3) binary MDS array codes that achieve asymptotically minimum repair bandwidth for d = k + 1.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Introduction to Special Section of international symposium on field-programmable gate arrays (FPGA) 2015

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acm TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2016年第4期9卷 1–2页

作者： Chen, Deming Univ Illinois Sch Elect Engn 410 Coordinated Sci Lab1308 W Main St Urbana IL 61801 USA

No abstract available.

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Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper 16

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGA...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Schmit, Herman Huang, Randy Intel Corporation San JoseCA United States

ISBN: (纸本)9781450341851

Intel's Xeon roadmap includes package-integrated FPGAs in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that FPGAs are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the FPGA. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications. © 2016 Authors.

关键词： field programmable gate arrays (FPGA)

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FPGA 2016 chairs' welcome

FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International ...

引用

FPGA 2016 - proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays 2016年 iii页

作者： Greene, Jonathan Chen, Deming Microsemi United States University of Illinois Urbana-Champaign Urbana-ChampaignIL United States

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Zynq-based SoC Implementation of an Induction Machine Control Algorithm 59

Zynq-based SoC Implementation of an Induction Machine Contro...

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59th IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Mohammadi, Danyal Daoud, Luka Rafla, Nader Ahmed-Zaid, Said Boise State Univ Dept Elect & Comp Engn Boise ID 83725 USA

ISBN: (纸本)9781509009169

In this paper, a new hardware/software design and implementation of an Induction Machine (IM) drive control topology is presented. Power electronic applications such as three-phase inverter require highly accurate switching frequency. This design uses a System on Chip (SoC) approach and implemented on a field programmable gate Array (FPGA). The on-chip processor is used for high level programing while the FPGA's programmable fabric is used to create precise gating signals for a three-phase inverter. These signals are generated in the hardware side of the design. Floating-point calculations and control flow of the whole design are managed by SoC. This method is suitable for any power electronic application where precise gating signals are required. The methodology used in this solution is explained and experimental results are presented.

关键词： field programmable gate arrays Registers Software Hardware Induction motors Inverters Switching frequency field programmable gate arrays Switching frequency Registers induction motors Inventors Computer hardware computer software three-phase inverter ELECTRONIC APPLICATION Induction machines

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On the Automation of High Level Synthesis of Convolutional Neural Networks 30

On the Automation of High Level Synthesis of Convolutional N...

引用

30th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Del Sozzo, Emanuele Solazzo, Andrea Miele, Antonio Santambrogio, Marco D. Politecn Milan Dipartimento Elett Informaz & Bioingn Milan Italy

ISBN: (纸本)9781509036820

Convolutional Neural Networks (CNNs) are a particular type of Artificial Neural Networks (ANNs) inspired by cells in the primary visual cortex of animals, and represent the state of the art in image recognition and classification. Nowadays, such supervised learning technique is very popular in Big Data analytics. In this context, due to the huge amount of data to be processed, it is crucial to find techniques to speed up the computation. In particular, the dataflow pattern of CNN algorithm results to be suitable for hardware acceleration. This paper proposes a framework to automatically generate a hardware implementation of CNNs on field programmable gate arrays (FPGAs), based on the High Level Synthesis (HLS) of configurable offline-trained networks.

关键词： field programmable gate arrays Convolutional Neural Networks High Level Synthesis

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