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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是201-210 订阅

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Look-Up Tables with Multiple Inputs for Secured-by-Design FPGAs 59

Look-Up Tables with Multiple Inputs for Secured-by-Design FP...

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59th IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Almohaimeed, Ziyad Sima, Mihai Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)9781509009169

We introduce a set of circuit techniques that make the dynamic and static power consumptions of multiple-input Look-Up Tables (LUT) independent of both the input data and FPGA configuration. This feature provides intrinsic robustness to dynamic and static power attacks. We also show that the proposed circuitry exhibits a monotonic response, which makes the FPGA robust to early evaluation attacks and those based on glitches. This quadruple robustness of the secured FPGA implementation is achieved while the FPGA configurability is fully maintained. The silicon area overhead is in line with the industrial and academic prior art, which means that the secured FPGA can be very attractive to cryptosystems developers.

关键词： multi-input field programmable gate arrays Tables circuit technique incoming data Power consumption

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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Automated Detection of Fault Sensitive Locations for Reconfiguration Attacks on programmable Logic 42

Automated Detection of Fault Sensitive Locations for Reconfi...

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42nd international symposium for Testing and Failure Analysis (ISTFA 2016)

作者： Lohrke, Heiko Scholz, Philipp Boit, Christian Tajik, Shahin Seifert, Jean-Pierre Tech Univ Berlin Dept High Frequency & Semicond Syst Tech Semicond Devices Berlin Germany Tech Univ Berlin Deutsch Telekom Innovat Labs Dept Software Engn & Theoret Comp Sci Secur Telecommun Berlin Germany

ISBN: (纸本)9781627081351;9781627081368

programmable logics, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), are widely used in security applications. In these applications cryptographic ciphers, physically unclonable functions (PUFs) and other security primitives are implemented on such platforms. These security primitives can be the target of fault injection attacks. One of the most powerful examples of fault injection techniques is laser fault injection (LFI), which can induce permanent or transient faults into the configuration memories of programmable logic. However, localization of fault sensitive locations on the chip requires reverse-engineering of the utilized building blocks, and therefore, is a tedious task. In this work, we propose an automated technique using readily available IC debug tools to map and profile the fault sensitive locations of programmable logic devices in a short period.

关键词： FPGA Security Laser Fault Injection Laser Fault Sensitivity programmable Logic Security Reverse Engineering

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Design of a Multi-Style and Multi-Frequency FPGA 24

Design of a Multi-Style and Multi-Frequency FPGA

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24th IFIP WG 10.5/IEEE international Conference on Very Large Scale Integration ( VLSI-SoC)

作者： Manoranjan, Jotham Vaddaboina Sajjan, Solomon Surya Tej Mano Gujari, Vivek B. Stevens, Kenneth S. Univ Utah Dept Elect & Comp Engn Salt Lake City UT 84112 USA

ISBN: (纸本)9781509035618

This paper presents an FPGA architecture capable of implementing relative timing based asynchronous designs. Modifications are made to a traditional synchronous FPGA architecture to make it asynchronous capable, while retaining its capability as a fully functional synchronous FPGA. Such a design permits multi-frequency implementations. A test FPGA fabric is developed and evaluated with the implementation of a MIPS processor. The asynchronous MIPS processor implemented on the designed FPGA provides a performance improvement of 1.7x while also providing a power improvement of 2.3x compared to the synchronous version of the MIPS implemented on a counterpart synchronous FPGA.

关键词： field programmable gate arrays (FPGA)

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A Power-Efficient and Non-volatile programmable Logic Array Based on Phase Change Memory

A Power-Efficient and Non-volatile Programmable Logic Array ...

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international Workshop on Information Data Storage / 10th international symposium on Optical Storage

作者： Du, Yuan Ye, Yong Kang, Yong Xia, Yangyang Song, Zhitang Chen, Bomy Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol State Key Lab Funct Mat Informat Shanghai 200050 Peoples R China Univ Chinese Acad Sci Beijing 10080 Peoples R China Shanghai Xinchu Integrated Circuit Incorp Shanghai 200122 Peoples R China

ISBN: (纸本)9781510600591

Recently, numerous efforts have been made on NVM-based field programmable gate arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can't be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of programmable Element is OFF.

关键词： PLA SRAM PCM low-power reconfigurable logic

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HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing 22

HRL: Efficient and Flexible Reconfigurable Logic for Near-Da...

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22nd IEEE international symposium on High-Performance Computer Architecture (HPCA)

作者： Gao, Mingyu Kozyrakis, Christos Stanford Univ Stanford CA 94305 USA Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467392112

The energy constraints due to the end of Dennard scaling, the popularity of in-memory analytics, and the advances in 3D integration technology have led to renewed interest in near-data processing (NDP) architectures that move processing closer to main memory. Due to the limited power and area budgets of the logic layer, the NDP compute units should be area and energy efficient while providing sufficient compute capability to match the high bandwidth of vertical memory channels. They should also be flexible to accommodate a wide range of applications. Towards this goal, NDP units based on fine-grained (FPGA) and coarse-grained (CGRA) reconfigurable logic have been proposed as a compromise between the efficiency of custom engines and the flexibility of programmable cores. Unfortunately, FPGAs incur significant area overheads for bit-level reconfiguration, while CGRAs consume significant power in the interconnect and are inefficient for irregular data layouts and control flows. This paper presents Heterogeneous Reconfigurable Logic (HRL), a reconfigurable array for NDP systems that improves on both FPGA and CGRA arrays. HRL combines both coarse-grained and fine-grained logic blocks, separates routing networks for data and control signals, and uses specialized units to effectively support branch operations and irregular data layouts in analytics workloads. HRL has the power efficiency of FPGA and the area efficiency of CGRA. It improves performance per Watt by 2.2x over FPGA and 1.7x over CGRA. For NDP systems running MapReduce, graph processing, and deep neural networks, HRL achieves 92% of the peak performance of an NDP system based on custom accelerators for each application.

关键词： field programmable gate arrays (FPGA)

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Automatic Generation of Efficient Accelerators for Reconfigurable Hardware 16

Automatic Generation of Efficient Accelerators for Reconfigu...

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43rd acm/IEEE Annual international symposium on Computer Architecture (ISCA)

作者： Koeplinger, David Prabhakar, Raghu Zhang, Yaqi Delimitrou, Christina Kozyrakis, Christos Olukotun, Kunle Stanford Univ Stanford CA 94305 USA Cornell Univ Ithaca NY 14853 USA Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467389471

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby increasing the importance of having good high-level FPGA design tools. However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration. We describe a design framework that addresses these challenges. We introduce a new representation of hardware using parameterized templates that captures locality and parallelism information at multiple levels of nesting. This representation is designed to be automatically generated from high-level languages based on parallel patterns. We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing. Our runtime estimation accounts for off-chip memory accesses. We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels. We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool. We compare the best-performing designs to optimized CPU code running on a server-grade 6 core processor and show speedups of up to 16.7x.

关键词： field programmable gate arrays Hardware Pipeline processing Space exploration Estimation Design tools

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On How to Improve FPGA-Based Systems Design Productivity via SDAccel 30

On How to Improve FPGA-Based Systems Design Productivity via...

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30th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Guidi, Giulia Reggiani, Enrico Di Tucci, Lorenzo Durelli, Gianluca Blott, Michaela Santambrogio, Marco D. Politecn Milan Dipartimento Elett Informaz & Bioingn Milan Italy

ISBN: (纸本)9781509036820

Custom hardware accelerators are widely used to improve the performance of software applications in terms of execution times and to reduce energy consumption. However the realization of an hardware accelerator and its integration in the final system is a difficult and error prone task. For this reason, both Industry and Academy are continuously developing Computer Aided Design (CAD) tools to assist the designer in the development process. Even if many of the steps have been nowadays automated, system integration and SW/HW interfaces definition and drivers generation are still almost completely manual tasks. The last tool released by Xilinx, however, aims at improving the hardware design experience by leveraging the OpenCL standard to enhance the overall productivity and to enable code portability. This paper provides an overview of the SDAccel potentiality comparing its design flow with other methodologies using two case studies from the Bioinformatics field: brain network and protein folding analysis.

关键词： field programmable gate arrays (FPGA)

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Design Guidelines for Embeded NoCs on FPGAs 17

Design Guidelines for Embeded NoCs on FPGAs

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17th international symposium on Quality Electronic Design (ISQED)

作者： Gamal, Noha Fahmy, Hossam Ismail, Yehea Mostafa, Hassan Mentor Graph Corp Wilsonville OR 97070 USA Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt Zewail City Sci & Technol CND Giza Egypt AUC New Cairo 11835 Egypt

ISBN: (纸本)9781509012138

Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-to-point interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), reduce the compile time and improve the system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gap between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), is the module with the smallest gaps: 1.8x area, 2.9x delay and 53x power. Switch has the largest gap: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power at the expense of no flexibility (reconfigurability). By comparing our results with same flow on ASIC-specific router, we show that using FPGA-specific NoCs design improves the utility by a factor of 3x in area with a slight increase in the delay.

关键词： field programmable gate arrays (FPGA)

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A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs 22

A Performance Analysis Framework for Optimizing OpenCL Appli...

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22nd IEEE international symposium on High-Performance Computer Architecture (HPCA)

作者： Wang, Zeke He, Bingsheng Zhang, Wei Jiang, Shunning Nanyang Technol Univ Singapore Singapore HKUST Clear Water Bay Hong Kong Peoples R China Cornell Univ Ithaca NY 14853 USA

ISBN: (纸本)9781467392112

Recently, FPGA vendors such as Altera and Xilinx have released OpenCL SDK for programming FPGAs. However, the architecture of FPGA is significantly different from that of CPU/GPU, for which OpenCL is originally designed. Tuning the OpenCL code for good performance on FPGAs is still an open problem, since the existing OpenCL tools and models designed for CPUs/GPUs are not directly applicable to FPGAs. In the paper, we present an FPGA-based performance analysis framework that can shed light on the performance bottleneck and thus guide the code tuning for OpenCL applications on FPGAs. Particularly, we leverage static and dynamic analysis to develop an analytical performance model, which has captured the key architectural features of FPGA abstractions under OpenCL. Then, we provide four programmer-interpretable metrics to quantify the performance potentials of the OpenCL program with input optimization combination for the next optimization step. We evaluate our framework with a number of user cases, and demonstrate that 1) our analytical performance model can accurately predict the performance of OpenCL programs with different optimization combinations on FPGAs, and 2) our tool can be used to effectively guide the code tuning on alleviating the performance bottleneck.

关键词： field programmable gate arrays (FPGA)

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