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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是211-220 订阅

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Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures 19

Quality of Service Driven Runtime Resource Allocation in Rec...

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19th IEEE international Conference on Computational Science and Engineering, 14th IEEE international Conference on Embedded and Ubiquitous Computing and 15th international symposium on Distributed Computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016

作者： Pogliani, Marcello Durelli, Gianluca C. Miele, Antonio Becker, Tobias Sanders, Peter Bolchini, Cristiana Santambrogio, Marco D. Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Italy Maxeler Technologies Ltd. United Kingdom

ISBN: (纸本)9781509035939

Heterogeneous System Architectures (HSA) are gaining importance in the High Performance Computing (HPC) domain due to increasing computational requirements coupled with energy consumption concerns, which conventional CPU architectures fail to effectively address. Systems based on field programmable gate Array (FPGA) recently emerged as an effective alternative to Graphical Processing Units (GPUs) for demanding HPC applications, although they lack the abstractions available in conventional CPU-based systems. This work tackles the problem of runtime resource management of a system using FPGA-based co-processors to accelerate multiprogrammed HPC workloads. We propose a novel resource manager able to dynamically vary the number of FPGAs allocated to each of the jobs running in a multi-accelerator system, with the goal of meeting a given Quality of Service metric for the running jobs measured in terms of deadline or throughput. We implement the proposed resource manager in a commercial HPC system, evaluating its behavior with representative workloads. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Synthesis and Evaluation of SHA-1 Algorithm Using Altera SDK for OpenCL 59

Synthesis and Evaluation of SHA-1 Algorithm Using Altera SDK...

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59th IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Janik, Ian Khalid, Mohammed A. S. Univ Windsor Dept Elect & Comp Engn RCIM Windsor ON N9B 3P4 Canada

ISBN: (纸本)9781509009169

This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL based designs. The paper presents results obtained by exploring the design space of the SHA-1 algorithm using AOCL. The FPGA accelerated program is also compared to an equivalent CPU version to measure the speedup. The HLS implementation managed to achieve a maximum throughput of 3033 Mbps. This speed is comparable to the HDL based designs in published literature. The CPU implementation has a maximum throughput of 217 Mbps, giving a 14 times speedup with the FPGA accelerated program.

关键词： Secure Hashing Algorithm Hardware design languages High-density lipoproteins Software Development Kit field programmable gate arrays hue lightness saturation Speeding Throughput cryptography algorithms synthesis

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IP Core Protection using Voltage-Controlled Side-Channel Receivers

IP Core Protection using Voltage-Controlled Side-Channel Rec...

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IEEE international symposium on Hardware Oriented Security and Trust (HOST)

作者： Samarin, Peter Lemke-Rust, Kerstin Paar, Christof Bonn Rhein Sieg Univ Appl Sci St Augustin Germany Ruhr Univ Bochum Bochum Germany

ISBN: (纸本)9781467388269

This paper presents a new method for protecting netlist-based Intellectual Property (IP) cores in FPGAs by actively using voltage-controlled side-channel receivers. The receivers are realized by modulating the supply voltage of the chip, while at the same time detecting these changes from within the chip using a ring oscillator. The levels of the supply voltage can be determined by constantly monitoring the frequency of the ring oscillator. To prove authorship of an IP core, the verifier authenticates himself to the core over the voltage side-channel and sends commands that limit the core's functionality. By monitoring the regular outputs of the overall system, it is possible to detect illegitimately used cores after repeatedly turning them on and off. The working principle of our method is demonstrated by a case study, in which we protect several IP cores and place them on a Spartan 3 FPGA, and show the steps necessary for successful proof of ownership verification.

关键词： field programmable gate arrays (FPGA)

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A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment 24

A Content Adapted FPGA Memory Architecture with Pattern Reco...

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24th IEEE international symposium on field-programmable Custom Computing Machines, FCCM 2016

作者： Harbaum, Tanja Seboui, Mahmoud Balzer, Matthias Becker, Jurgen Weber, Marc Germany Germany

ISBN: (纸本)9781509023561

Modern high-energy physics experiments such as the Compact Muon Solenoid experiment at CERN produce an extraordinary amount of data every 25ns. To handle a data rate of more than 50Tbit/s a multi-level trigger system is required, which reduces the data rate. Due to the increased luminosity after the Phase-II-Upgrade of the LHC, the CMS tracking system has to be redesigned. The current trigger system is unable to handle the resulting amount of data after this upgrade. Because of the latency of a few microseconds the Level 1 Track Trigger has to be implemented in hardware. State-of-the-art pattern recognition filter the incoming data by template matching on ASICs with a content addressable memory architecture. An implementation on an FPGA, which replaces the content addressable memory of the ASIC, has not been possible so far. This paper presents a new approach to a content addressable memory architecture, which allows an implementation of an FPGA based design. By combining filtering and track finding on an FPGA design, there are many possibilities of adjusting the two algorithms to each other. There is more flexibility enabled by the FPGA architecture in contrast to the ASIC. The presented design minimizes the stored data by logic to optimally utilize the available resources of an FPGA. Furthermore, the developed design meets the strong timing constraints and possesses the required properties of the content addressable memory. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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An Online Tool to Design Highly Parametrized Optimized Encoders and Decoders 19

An Online Tool to Design Highly Parametrized Optimized Encod...

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作者： Dasygenis, Minas Department of Informatics and Telecommunications Engineering University of Western Macedonia Kozani50100 Greece

ISBN: (纸本)9781509035939

The rising complexity of embedded digital applications and the growing importance of time-to-market require powerful modeling methods and tools to automate the design and implementation process. Electronic design automation (EDA) tools provide the required assistance to every design team, increasing its efficiency and helping meet the hard time to market constraints. Encoders and decoders are an essential module of every programmable architecture. Even though there are EDA tools to generate intellectual property (IP) blocks for many circuits, to the best of our knowledge, there are no tools to design IP blocks of such modules. We noticed this absence and we designed a tool to create verified and optimized HDL description of such circuits and furthermore, we have made it available via our public web server. Our IP blocks are vendor neutral and can be synthesized either on ASIC or on FPGA. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 762 Mhz. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Multiple FPGAs based prototyping and debugging with complete design flow 11

Multiple FPGAs based prototyping and debugging with complete...

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11th international Design and Test symposium (IDT)

作者： Azeem, Muhammad Moazam Chotin-Avot, Roselyne Farooq, Umer Ravoson, Maminionja Mehrez, Habib UPMC Univ Paris 06 Sorbonne Univ LIP6 Paris France

ISBN: (纸本)9781509049004

Multiple FPGA-based prototyping plays an important role in the design and verification process due to their low cost and high execution speed. However, there is a need to optimize the configuration flow of this multiple FPGA based prototyping. In this paper, we address the partitioning of large designs and propose a debugging methodology for these partitioned designs using Signal Tap II embedded logic analyzer by Quartus tool of Altera. Usually SignalTap II tool is used to debug design implemented on single FPGA and this logic analyzer debugs FPGA device by probing the states of internal signals without using external debug equipment. However, we use SignalTap II logic analyzer for large designs on multiple FPGAs and we facilitate the debugging methodology for thousands of signals under consideration. We propose the debugging of large designs after partitioning by developing the techniques to trace the required signals under test through multiple FPGAs without using FPGA internal memory. We have generated various large benchmarks as well and tested them for multiple FPGA-based prototyping.

关键词： field programmable gate arrays (FPGA)

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2013年 iii页

作者： Hutchings, Brad Betz, Vaughn Brigham Young University United States University of Toronto Canada

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FPGA Based Sensor Integration and Communication Protocols for Automated Robot Control in Linear Welding 13

FPGA Based Sensor Integration and Communication Protocols fo...

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13th Latin American Robotics symposium / 4th Brazilian Robotics symposium (LARS/SBR)

作者： Steffens, Cristiano Rafael Huettner, Valquiria Leonardo, Bruno Quaresma da Rosa, Vagner Santos da Costa Botelho, Silvia Silva Fed Univ Rio Grande Computat Sci Ctr C3 Av Italia Km 9 Rio Grande RS Brazil

ISBN: (纸本)9781509036561

Electric arc welding is a complex task that is mainly hand-operated in shop floors nowadays. A high degree of process control is necessary to meet the international standards for fusion welding. Focused on this application case, we designed a camera interface that integrates a Terasic TRDB-D5M CMOS camera and an Altera DE0-Nano FPGA board which are used for image acquisition on a Vision-Based Measurement (VBM) system that executes on a computer. Given the board limitations in terms of memory, clock, and connectivity many features and protocols were developed from scratch. We present a system level modeling and synthesis and the integration to the whole digital linear welding system, using only 28% of the FPGA's slices. Results show the approach is a viable option to automate the process that is currently widely adopted in industry.

关键词： field programmable gate arrays (FPGA)

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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

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49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Stochastic-Based Spin-programmable gate Array with Emerging MTJ Device Technology (Abstract Only) 16

Stochastic-Based Spin-Programmable Gate Array with Emerging ...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yu Bai Mingjie Lin University of Central Florida Orlando FL USA

ISBN: (纸本)9781450338561

This paper describes the stochastic-based Spin-programmable gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

关键词： stochastic fpga emerging devices

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