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A separation and protection scheme for on-chip memory blocks in FPGAs

A separation and protection scheme for on-chip memory blocks...

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2016 IEEE international symposium on Hardware Oriented Security and Trust, HOST 2016

作者： Rivera, Luis Ramirez Wang, Xiaofang Chasaki, Danai Dept. of Electrical and Computer Engineering Villanova University VillanovaPA19085 United States

ISBN: (纸本)9781467388252

State-of-the-art FPGAs are quickly evolving into a complete system-on-chip (SoC) platform with aggressive integration of high-performance hard processor cores, gigabytes of dedicated memory blocks, and many commonly used peripherals. As FPGAs increasingly find their way into many critical and sensitive applications, including speeding cryptographic algorithms, security concerns about themselves start mounting. Current countermeasures mostly target hardware trojans, cloning, side-channel attacks, and reverse engineering. Little attention has been devoted to securing dedicated on-chip memory blocks. Moreover, the dynamic reconfigurability nature of FPGAs makes static-only approaches less effective and less efficient. In this paper, we present the design and implementation of a runtime protection scheme for FPGA on-chip memory blocks. To secure on-chip memory inside FPGAs, careful design choices must be taken because of their very low latency and simple flat memory model. A series of rules, called security policies are made. These policies are enforced by a reference monitor who mediates the communications between the intellectual properties (IP) or modules that requires the memory, and the memory itself. The memory security scheme is an implementation of a security kernel, enforced by a series of security policies, with a specific policy algorithm which tells four security monitors to control the memory accesses between IPs and the on-chip memory inside the FPGA used. The results on a Xilinx Virtex-6 FPGA board show that the security monitors themselves are successful in preventing unauthorized accesses from IPs that are marked as untrusted while allowing full access from other IPs that are marked as trusted, without incurring on a serious area or latency penalty. Also, by preventing the access from untrusted IPs and marking connections as not traversable, the connections between the untrusted IPs and the memory that it has to share with trusted IPs are secured. © 201

关键词： field programmable gate arrays (FPGA)

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Superoptimized memory subsystems for streaming applications 15

Superoptimized memory subsystems for streaming applications

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wingbermuehle, Joseph G. Cytron, Ron K. Chamberlain, Roger D. Dept. of Computer Science and Engineering Washington University in St. Louis United States

ISBN: (纸本)9781450333153

Because main memory is many times slower than modern processor cores, deep, multi-level cache hierarchies are ubiquitous in computers today. Similarly, applications deployed on ASICs and FPGAs are often hindered by slow external memories. Therefore, to achieve good performance, hardware designers must optimize main memory usage. Unfortunately, this process is often labor intensive and fails to explore the full range of potential memory designs. To address this issue for applications expressed in a streaming manner, we show that it is possible to generate automatically a superoptimized memory subsystem that can be deployed on an FPGA such that it performs better than a general-purpose memory subsystem. Rather than explore only simple memory subsystems, our superoptimizer is capable of exploring extremely complex designs consisting of multi-level caches and other components. Finally, we show that it is possible to deploy applications with superoptimized memory subsystems with minimal additional effort while achieving significant performance improvements over a naive memory subsystem.

关键词： field programmable gate arrays (FPGA)

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Enhancements in UltraScale CLB architecture 15

Enhancements in UltraScale CLB architecture

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chandrakar, Shant Gaitonde, Dinesh Bauer, Trevor Xilinx Inc. Hyderabad India Xilinx Inc. San JoseCA United States Xilinx Inc. LongmontCO United States

ISBN: (纸本)9781450333153

Each generation of FPGA architecture benefits from optimizations around its technology node and target usage. In this paper, we discuss some of the changes made to the CLB for Xilinx's 20nm UltraScale product family. We motivate those changes and demonstrate better results than previous CLB architectures on a variety of metrics. We show that, in demanding scenarios, logic placed in an UltraScale device requires 16% less wirelength than 7-series. Designs mapped to UltraScale devices also require fewer logic tiles. In this paper, we demonstrate the utilization benefits of the Ultra-Scale CLB attributed to certain CLB enhancements. The enhancements described herein result in an average packing improvement of 3% for the example design suite. We also show that the UltraScale architecture handles aggressive, tighter packing more gracefully than previous generations of FPGA. These significant reductions in wirelength and CLB counts translate directly into power, performance and ease-of-use benefits.

关键词： field programmable gate arrays (FPGA)

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Fine-grained interconnect synthesis 15

Fine-grained interconnect synthesis

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Rodionov, Alex Biancolin, David Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Canada

ISBN: (纸本)9781450333153

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis tool that automates this process and focuses on the interconnect needs in the fine-grained (sub-IP-block) design space. Here there are several issues that prior research and tools do not address well: the need to have fixed, deterministic latency between communicating units (to enable high-performance local communication without the area overheads of latency-insensitivity), and the ability to avoid generating un-necessary arbitration hardware when the application design can avoid it. Using a design example, our tool generates interconnect that requires 72% fewer lines of specification code than a hand-written Verilog implementation, which is a 33% overall reduction for the entire application. The resulting system, while requiring 4% more total functional and interconnect area, achieves the same performance. We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 17%/57% logic/memory area savings.

关键词： field programmable gate arrays (FPGA)

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Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only) 16

Re-targeting Optimization Sequences from Scalar Processors t...

引用

proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Ronak Kogta Suresh Purini Ajit Mathew International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450338561

A high-level synthesis compiler translates a source program written in a high level programming language such as C or SystemC into an equivalent circuit. The performance of the generated circuit in terms of metrics such as area, frequency and clock cycles depends on the compiler optimizations enabled and their order of application. Finding an optimal sequence for a given program is a hard combinatorial optimization problem. In this paper, we propose a practical and search time efficient technique for finding a near-optimal sequence for a given program. The main idea is to strike a balance between the search for a universally good sequence (like that of O3) which works for all programs vis-a-vis finding a good sequence on a per-program basis. Towards that, we construct a rich downsampled sequence set, which caters to different program classes, from the unbounded optimization sequence space by applying heuristic search algorithms on a set of Microkernel benchmark programs. The optimization metric that we use while constructing the downsampled sequence set is the execution time on a scalar processor. Given a new program, we try all the sequences from the downsampled sequence setand pick the best. Applying this technique in the LegUp high-level synthesis compiler, we are able to obtain 23% and 40% improvement on CHStone and Machsuite benchmark programs respectively. We also propose techniques to further reduce the size of the downsampled sequence set to improve the sequence search time.

关键词： high level synthesis optimization compilers

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InTime: A machine learning approach for efficient selection of FPGA CAD tool parameters 15

InTime: A machine learning approach for efficient selection ...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Kapre, Nachiket Ng, Harnhua Teo, Kirvy Naude, Jaco Nanyang Technological University Singapore Singapore Plunify Inc. Singapore Singapore

ISBN: (纸本)9781450333153

FPGA CAD tool parameters controlling synthesis optimizations, place and route effort, mapping criteria along with user-supplied physical constraints can affect timing results of the circuit by as much as 70% without any change in original source code. A correct selection of these parameters across a diverse set of benchmarks with varying characteristics and design goals is challenging. The sheer number of parameters and option values that can be selected is large (thousands of combinations for modern CAD tools) with often conflicting interactions. In this paper, we present InTime, a machinelearning approach supported by a cloud-based (or clusterbased) compilation infrastructure for automating the selection of these parameters effectively to minimize timing costs. InTime builds a database of results from a series of preliminary runs based on canned configurations of CAD options. It then learns from these runs to predict the next series of CAD tool options to improve timing results. Towards the end, we rely on a limited degree of statistical sampling of certain options like placer and synthesis seeds to further tighten results. Using our approach, we show 70% reduction in final timing results across industrial benchmark problems for the Altera CAD flow. This is 30% better than vendor-supplied design space exploration tools that attempts a similar optimization using canned heuristics. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Mapping-aware constrained scheduling for LUT-based FPGAs 15

Mapping-aware constrained scheduling for LUT-based FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Tan, Mingxing Dai, Steve Gupta, Udit Zhang, Zhiru School of Electrical and Computer Engineering Cornell University IthacaNY United States

ISBN: (纸本)9781450333153

Scheduling plays a central role in high-level synthesis, as it inserts clock boundaries into the untimed behavioral model and greatly impacts the performance, power, and area of the synthesized circuits. While current scheduling techniques can make use of pre-characterized delay values of individual operations, it is difficult to obtain accurate timing estimation on a cluster of operations without considering technology mapping. This limitation is particularly pronounced for FPGAs where a large logic network can be mapped to only a few levels of look-up tables (LUT). In this paper, we propose MAPS, a mapping-aware constrained scheduling algorithm for LUT-based FPGAs. Instead of simply summing up the estimated delay values of individual operations, MAPS jointly performs technology mapping and scheduling, creating the opportunity for more aggressive operation chaining to minimize latency and reduce area. We show that MAPS can produce a latency-optimal solution, while supporting a variety of design timing requirements expressed in a system of difference constraints. We also present an efficient incremental scheduling technique for MAPS to effectively handle resource constraints. Experimental results with real-life benchmarks demonstrate that our proposed algorithm achieves very promising improvements in performance and resource usage when compared to a state-of-the-art commercial high-level synthesis tool targeting Xilinx FPGAs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Application of specific delay window routing for timing optimization in FPGA designs 15

Application of specific delay window routing for timing opti...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wegley, Evan Zhang, Qinhai Lattice Semiconductor Corporation 2115 O'Nel Drive San JoseCA95131 United States

ISBN: (纸本)9781450333153

In addition to optimizing for timing performance and routability, commercial FPGA routing engines must also support various timing constraints enabling the designer to fine tune aspects of their design. The many intricacies of commercial FPGA architectures add difficulty to the problem of supporting such constraints. In this paper, we show how the method of specific delay window routing can be applied to optimize for these various timing constraints constituting both long-and short-path requirements. Additionally, we enhance existing methods of routing according to specified delay by using dual wave expansion instead of single wave expansion with target delay estimation in order to improve accuracy and support sparser, more varied interconnect structures. Our results show that specific delay window routing is well-suited for optimization targeting a variety of timing constraints, and that using dual wave expansion to eliminate the estimation part of the router's delay cost function enables the router to support tighter timing constraints. For a suite of designs with known hold timing violations, we found that the dual wave approach can correct all such violations, whereas the single wave approach failed to correct the hold timing violations for several designs. Furthermore, for a suite of designs with maximum skew constraints of 250 ps on certain nets and buses, the dual wave approach met the constraints for all designs, whereas the single wave approach failed to meet the constraints for a majority of the designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Delay-bounded routing for shadow registers 15

Delay-bounded routing for shadow registers

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Hung, Eddie Levine, Joshua M. Stott, Edward Constantinides, George A. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College London United Kingdom Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9781450333153

The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve

关键词： field programmable gate arrays (FPGA)

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Energy-efficient discrete signal processing with field programmable analog arrays (FPAAs) 15

Energy-efficient discrete signal processing with field progr...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Bai, Yu Lin, Mingjie Department of Electrical Engineering and Computer Science University of Central Florida OrlandoFL32765 United States

ISBN: (纸本)9781450333153

Large-scale field programmable analog array (FPAA) devices have made analog and analog-digital signal processing techniques accessible to a much wider community. However, largely due to its severe resource constraints, high noise sensitivity, and enormous design space, reconfigurable analog computing remains a niche in the DSP application space. In this paper, we develop a probabilistic-based methodology for designing and implementing the analog computing engines that specifically target at energy-efficient signal processing systems. We will first demonstrate how to decompose a given DSP application into various functional modules within the framework of probabilistic-based processing. Furthermore, we will show how these individual functional modules can be easily mapped to the limited selection of analog blocks found in an commercially available FPAA device: the PSoC chip platform from Cypress. To keep our study concrete, our implementation example focuses on the 1-D convolution module, a fundamental algorithmic building block in many applications of computer vision and artificial intelligence. In the end, we construct a complete image processing system based on the PSoC chip platform, and use the application of image key point extraction to demonstrate that our proposed approach to reconfigurable analog computing has considerable advantages in hardware usage, energy efficiency, and computing robustness over the traditional DSP approaches. © Copyright acm.

关键词： Digital signal processing

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