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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Energy and memory efficient mapping of bitonic sorting on FPGA 15

Energy and memory efficient mapping of bitonic sorting on FP...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chen, Ren Siriyal, Sruja Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles90089 United States

ISBN: (纸本)9781450333153

Parallel sorting networks are widely employed in hardware implementations for sorting due to their high data paral- lelism and low control overhead. In this paper, we propose an energy and memory efficient mapping methodology for implementing bitonic sorting network on FPGA. Using this methodology, the proposed sorting architecture can be built for a given data parallelism while supporting continuous data streams. We propose a streaming permutation network (SPN) by "folding" the classic Clos network. We prove that the SPN is programmable to realize all the interconnection patterns in the bitonic sorting network. A low cost design for sorting with minimal resource usage is obtained by reusing one SPN. We also demonstrate a high throughput design by trading off area for performance. With a data parallelism of p (2≤ p≤ N= log2 N), the high throughput design sorts an N-key sequence with latency O(N=p), throughput (# of keys sorted per cycle) O(p) and uses O(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) of O(p=N). Another noteworthy feature of the high throughput design is that only single-port memory rather than dual-port memory is required for processing continu- ous data streams. This results in 50% reduction in memory consumption. Post place-and-route results show that our architecture demonstrates 1.3x∼1.6x improvment in energy efficiency and 1.5x∼5.3x better memory efficiency compared with the state-of-the-art designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Sleep stage classification with stochastic Bayesian inference

Sleep stage classification with stochastic Bayesian inferenc...

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IEEE international symposium on Nanoscale Architectures (NANOARCH)

作者： L. E. Calvet J. S. Friedman D. Querlioz P. Bessière J. Droulez Centre de Nanosciences et de Nanotechnologies Université Paris-Saclay Orsay France Institut des Systèmes Intelligents et de Robotique Université Pierre et Marie Curie-CNRS Paris France

ISBN: (纸本)9781467389273

The design of electronic circuits that can realize Bayesian inference is an important goal for exploiting machine learning in a fast and efficient way. We recently developed a novel architecture based on stochastic computation with Muller C-elements that can realize a circuit level naïve Bayes inference. This technique can be implemented using low power nanodevices exhibiting faults and device variations. Here we show how a more complex classification problem can be transformed into a simple circuit using this framework where an effective classification can be obtained with a minimal amount of information. This suggests that substantially smaller spatial footprints for portable devices could ultimately be achieved.

关键词： Decision support systems field programmable gate arrays Manuals Terminology

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Hardware Friendly Adaptive Support-Weight Approach for Stereo Matching

Hardware Friendly Adaptive Support-Weight Approach for Stere...

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international symposium on Optoelectronic Technology and Application 2016(OTA 2016)——Conf.6 Robot Sensing and Advanced Control

作者： Zuoxun Hou Pei Han Hongwei Zhang Ran An Beijing Institute of Space Mechanics and Electricity Technology and Engineering Center for Space Utilization Chinese Academy of Sciences

In this paper, the hardware friendly adaptive support-weight approach is proposed to simplify the weight calculation process of the standard approach, which employs the support region to simplify the

ISBN: (纸本)9781510607729

In this paper, the hardware friendly adaptive support-weight approach is proposed to simplify the weight calculation process of the standard approach, which employs the support region to simplify the

关键词： Binocular vision Hardware Friendly Adaptive Support-Weight Binocular vision hardware architecture Self tuning Computer hardware test standards field programmable gate arrays Simplify

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Extra-Functional Properties Composability for Embedded Systems Partitioning

Extra-Functional Properties Composability for Embedded Syste...

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international acm SIGSOFT symposium on Component-Based Software Engineering (CBSE)

作者： Gaetana Sapienza Séverine Sentilles Ivica Crnkovic Tiberiu Seceleanu ABB Corporate Research and Mälardalen University Västerås Sweden Mälardalen University Västerås Sweden Chalmers and Mälardalen University Gothenburg and Västerås Sweden

ISBN: (纸本)9781509025701

Modern embedded systems utilize the advances in heterogeneous platforms that enable implementing functions in software (SW) and hardware (HW) components. A proper configuration of SW and HW components can significantly improve the values of the extra-functional properties such as performance and energy savings. However, due to increasing application complexity, it is difficult to find the best combination of HW and SW components. The problem basically boils down to calculate, for a given architecture, the system properties from the components' ones. In this paper, we address the problem of composability of EFPs at system level. Although in general this is not a solvable problem, we present that, under strictly specified constraints, it is possible to compose the system EFPs starting from the component ones. We start by detailing constraints related to the system architecture, platform and process development and, based on these constraints, we provide composition rules for different types of EFPs. We demonstrate the results through an industrial example.

关键词： Embedded systems Semantics Ports (Computers) field programmable gate arrays Software engineering Electronic mail

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Optimizing FPGA-based accelerator design for deep convolutional neural networks 15

Optimizing FPGA-based accelerator design for deep convolutio...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Zhang, Chen Li, Peng Sun, Guangyu Guan, Yijin Xiao, Bingjun Cong, Jason Center for Energy-Efficient Computing and Applications Peking University China Computer Science Department University of California Los Angeles United States PKU UCLA Joint Research Institute in Science and Engineering United States

ISBN: (纸本)9781450333153

Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapid growth of modern applications based on deep learning algorithms has further improved research and implementations. Especially, various accelerators for deep CNN have been proposed based on FPGA platform because it has advantages of high performance, reconfigurability, and fast development round, etc. Although current FPGA accelerators have demonstrated better performance over generic processors, the accelerator design space has not been well exploited. One critical problem is that the computation throughput may not well match the memory bandwidth provided an FPGA platform. Consequently, existing approaches cannot achieve best performance due to underutilization of either logic resource or memory bandwidth. At the same time, the increasing complexity and scalability of deep learning applications aggravate this problem. In order to overcome this problem, we propose an analytical design scheme using the rooine model. For any solution of a CNN design, we quantitatively analyze its computing throughput and required memory bandwidth using various optimization techniques, such as loop tiling and transformation. Then, with the help of rooine model, we can identify the solution with best performance and lowest FPGA resource requirement. As a case study, we implement a CNN accelerator on a VC707 FPGA board and compare it to previous approaches. Our implementation achieves a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.

关键词： field programmable gate arrays (FPGA)

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Fused-layer CNN accelerators 49

Fused-layer CNN accelerators

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IEEE/acm international symposium on Microarchitecture (MICRO)

作者： Manoj Alwani Han Chen Michael Ferdman Peter Milder Stony Brook University

ISBN: (纸本)9781509035090

Deep convolutional neural networks (CNNs) are rapidly becoming the dominant approach to computer vision and a major component of many other pervasive machine learning tasks, such as speech recognition, natural language processing, and fraud detection. As a result, accelerators for efficiently evaluating CNNs are rapidly growing in popularity. The conventional approaches to designing such CNN accelerators is to focus on creating accelerators to iteratively process the CNN layers. However, by processing each layer to completion, the accelerator designs must use off-chip memory to store intermediate data between layers, because the intermediate data are too large to fit on chip. In this work, we observe that a previously unexplored dimension exists in the design space of CNN accelerators that focuses on the dataflow across convolutional layers. We find that we are able to fuse the processing of multiple CNN layers by modifying the order in which the input data are brought on chip, enabling caching of intermediate data between the evaluation of adjacent CNN layers. We demonstrate the effectiveness of our approach by constructing a fused-layer CNN accelerator for the first five convolutional layers of the VGGNet-E network and comparing it to the state-of-the-art accelerator implemented on a Xilinx Virtex-7 FPGA. We find that, by using 362KB of on-chip storage, our fused-layer accelerator minimizes off-chip feature map data transfer, reducing the total transfer by 95%, from 77MB down to 3.6MB per image.

关键词： System-on-chip Bandwidth Random access memory Neural networks Convolution field programmable gate arrays Data transfer

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From high-level deep neural models to FPGAs 49

From high-level deep neural models to FPGAs

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IEEE/acm international symposium on Microarchitecture (MICRO)

作者： Hardik Sharma Jongse Park Divya Mahajan Emmanuel Amaro Joon Kyung Kim Chenkai Shao Asit Mishra Hadi Esmaeilzadeh Alternative Computing Technologies (ACT) Lab Georgia Institute of Technology Intel Corporation

ISBN: (纸本)9781509035090

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAs are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAs is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAs' limited on-chip storage makes DNN acceleration using FPGAs more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAs, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design.

关键词： field programmable gate arrays Hardware Schedules Weaving Acceleration System-on-chip Computational modeling

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A cloud-scale acceleration architecture 49

A cloud-scale acceleration architecture

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IEEE/acm international symposium on Microarchitecture (MICRO)

作者： Adrian M. Caulfield Eric S. Chung Andrew Putnam Hari Angepat Jeremy Fowers Michael Haselman Stephen Heil Matt Humphrey Puneet Kaur Joo-Young Kim Daniel Lo Todd Massengill Kalin Ovtcharov Michael Papamichael Lisa Woods Sitaram Lanka Derek Chiou Doug Burger Microsoft Corporation

ISBN: (纸本)9781509035090

Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware (efficiency) with the economic benefits of homogeneity (manageability). In this paper we propose a new cloud architecture that uses reconfigurable logic to accelerate both network plane functions and applications. This Configurable Cloud architecture places a layer of reconfigurable logic (FPGAs) between the network switches and the servers, enabling network flows to be programmably transformed at line rate, enabling acceleration of local applications running on the server, and enabling the FPGAs to communicate directly, at datacenter scale, to harvest remote FPGAs unused by their local servers. We deployed this design over a production server bed, and show how it can be used for both service acceleration (Web search ranking) and network acceleration (encryption of data in transit at high-speeds). This architecture is much more scalable than prior work which used secondary rack-scale networks for inter-FPGA communication. By coupling to the network plane, direct FPGA-to-FPGA messages can be achieved at comparable latency to previous work, without the secondary network. Additionally, the scale of direct inter-FPGA messaging is much larger. The average round-trip latencies observed in our measurements among 24, 1000, and 250,000 machines are under 3, 9, and 20 microseconds, respectively. The Configurable Cloud architecture has been deployed at hyperscale in Microsoft's production datacenters worldwide.

关键词： field programmable gate arrays Servers Acceleration Computer architecture Hardware Production Cloud computing

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The Digital Bidirectional Function as a Hardware Security Primitive: Architecture and Applications 20

The Digital Bidirectional Function as a Hardware Security Pr...

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IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781467380096

Security and low power have emerged to become two essential requirements to modern design. In this paper, we have proposed a new hardware security primitive: digital bidirectional function (DBF) designed on FPGA to meet both criteria. The DBF has two forms of functions and implements two mappings of opposite directions. The DBF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. In terms of applications, we demonstrate how DBF is applied in the protocol of secure message transfer and compare its power/bandwidth consumption with other cryptographic approaches. Our results indicate that the energy consumption of DBF outperforms the traditional ciphers by averagely two to three orders of magnitude.

关键词： DESIGN BASIS FIRES hardware security modern design energy consumption message passing field programmable gate arrays Primitive Bidirectional

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FPGA'12 - proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

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2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy FPGA-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on FPGA;incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on FPGAs;saturating the transceiver bandwidth: switch fabric design on FPGAs;limit study of energy & delay benefits of component-specific routing;impact of FPGA architecture on resource sharing in high-level synthesis;and securing netlist-level FPGA design through exploiting process variation and degradation.

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