检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

610 篇 会议
32 篇 期刊文献

馆藏范围

642 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

551 篇 工学
- 495 篇 计算机科学与技术...
- 283 篇 软件工程
- 224 篇 电子科学与技术（可...
- 184 篇 电气工程
- 91 篇 信息与通信工程
- 36 篇 控制科学与工程
- 34 篇 动力工程及工程热...
- 24 篇 机械工程
- 15 篇 生物工程
- 12 篇 仪器科学与技术
- 9 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 材料科学与工程（可...
- 7 篇 生物医学工程（可授...
- 6 篇 测绘科学与技术
- 4 篇 光学工程
- 3 篇 农业工程
199 篇 理学
- 165 篇 数学
- 34 篇 物理学
- 19 篇 统计学（可授理学、...
- 16 篇 生物学
- 8 篇 系统科学
- 6 篇 化学
54 篇 管理学
- 46 篇 管理科学与工程(可...
- 30 篇 工商管理
- 9 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 农学
2 篇 教育学
1 篇 医学

主题

295 篇 field programmab...
172 篇 field programmab...
65 篇 clocks
64 篇 signal processin...
64 篇 estimation
63 篇 modulation
63 篇 ofdm
63 篇 filtration
30 篇 fpga
8 篇 routing
8 篇 optimization
8 篇 field-programmab...
7 篇 fpgas
7 篇 systolic arrays
7 篇 high-level synth...
7 篇 hardware
7 篇 field-programmab...
7 篇 reconfigurable c...
5 篇 programmable log...
5 篇 logic gates

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
5 篇 intel corporatio...
4 篇 univ british col...
4 篇 tsinghua univers...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 nanyang technol ...
3 篇 computer science...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 nanyang technol ...
3 篇 xilinx inc. san ...
3 篇 politecn milan d...
3 篇 school of comput...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
10 篇 chen deming
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 kiah han mao
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...

语言

635 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是261-270 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Accelerating frequent item counting with FPGA 14

Accelerating frequent item counting with FPGA

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Sun, Yuliang Wang, Zilong Huang, Sitao Wang, Lanjun Wang, Yu Luo, Rong Yang, Huazhong E.E. Dept. TNLIST Tsinghua University China IBM Research-China China

ISBN: (纸本)9781450326711

Frequent item counting is one of the most important operations in time series data mining algorithms, and the space saving algorithm is a widely used approach to solving this problem. With the rapid rising of data input speeds, the most challenging problem in frequent item counting is to meet the requirement of wire-speed processing. In this paper, we propose a streaming oriented PE-ring framework on FPGA for counting frequent items. Compared with the best existing FPGA implementation, our basic PE-ring framework saves 50% lookup table resources cost and achieves the same throughput in a more scalable way. Furthermore, we adopt SIMD-like cascaded filter for further performance improvements, which outperforms the previous work by up to 3.24 times in some data distributions.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

引用

acm/sigda international symposium on field programmable gate arrays - FPGA 2012年 iii页

作者： Compton, Katherine Hutchings, Brad University of Wisconsin Madison WI United States Brigham Young University United States

来源：评论

学校读者我要写书评

暂无评论

A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

来源：评论

学校读者我要写书评

暂无评论

OmpSs@zynq all-programmable soc ecosystem

OmpSs@zynq all-programmable soc ecosystem

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Filgueras, Antonio Gil, Eduard Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Langer, Jan Noguera, Juanjo Vissers, Kees Barcelona Supercomputing Center Spain Universitat Politecnica de Catalunya Spain Xilinx Research Lab United States

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely inuenced the recently appeared OpenMP 4.0 specication. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benets DLP, ILP and TLP parallelisms in order to eciently exploit the new tech-nology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous ex-ecution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： System-on-chip

来源：评论

学校读者我要写书评

暂无评论

FPGA place & route challenges 14

FPGA place & route challenges

引用

2014 acm international symposium on Physical Design, ISPD 2014

作者： Aggarwal, Rajat Xilinx Inc 2100 Logic Dr San Jose CA 95124 United States

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

ISBN: (纸本)9781450325929

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Rent's rule based FPGA packing for routability optimization 14

Rent's rule based FPGA packing for routability optimization

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Feng, Wenyi Greene, Jonathan Vorwerk, Kristofer Pevzner, Val Kundu, Arun Microsemi Corporation 3870 N 1st Street San Jose CA 95134 United States

ISBN: (纸本)9781450326711

Packing is a critical step in the CAD flow for cluster-based FPGA architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for FPGA packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Wordwidth, instructions, looping, and virtualization the role of sharing in absolute energy minimization 14

Wordwidth, instructions, looping, and virtualization the rol...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450326711

When are FPGAs more energy ecient than processors? This question is complicated by technology factors and the wide range of application characteristics that can be ex-ploited to minimize energy. Using a wire-dominated en-ergy model to estimate the absolute energy required for pro-grammable computations, we determine when spatially or-ganized programmable computations (FPGAs) require less energy than temporally organized programmable computa-tions (processors). The point of crossover will depend on the metal layers available, the locality, the SIMD wordwidth regularity, and the compactness of the instructions. When the Rent Exponent, p, is less than 0.7, the spatial design is always more energy ecient. When p = 0:8, the technology oers 8-metal layers for routing, and data can be organized into 16b words and processed in tight loops of no more than 128 instructions, the temporal design uses less energy when the number of LUTs is greater than 64K. We further show that heterogeneous multicontext architectures can use even less energy than the p = 0:8, 16b word temporal case.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Hardware acceleration of database operations 14

Hardware acceleration of database operations

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Casper, Jared Olukotun, Kunle Pervasive Parallelism Laboratory Stanford University United States

ISBN: (纸本)9781450326711

As the amount of memory in database systems grows, en-tire database tables, or even databases, are able to t in the system's memory, making in-memory database operations more prevalent. This shift from disk-based to in-memory database systems has contributed to a move from row-wise to columnar data storage. Furthermore, common database workloads have grown beyond online transaction process-ing (OLTP) to include online analytical processing and data mining. These workloads analyze huge datasets that are of-ten irregular and not indexed, making traditional database operations like joins much more expensive. In this paper we explore using dedicated hardware to ac-celerate in-memory database operations. We present hard-ware to accelerate the selection process of compacting a sin-gle column into a linear column of selected data, joining two sorted columns via merging, and sorting a column. Finally, we put these primitives together to accelerate an entire join operation. We implement a prototype of this system using FPGAs and show substantial improvements in both absolute throughput and utilization of memory bandwidth. Using the prototype as a guide, we explore how the hardware resources required by our design change with the desired throughput.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Square-rich fixed point polynomial evaluation on FPGAs 14

Square-rich fixed point polynomial evaluation on FPGAs

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Xu, Simin Fahmy, Suhaib A. McLoughlin, Ian V. Xilinx Asia Pacific Singapore School of Computer Engineering Nanyang Technological University Singapore School of Information Science and Technology University of Science and Technology of China China

ISBN: (纸本)9781450326711

Polynomial evaluation is important across a wide range of application domains, so signicant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial com-putation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an effcient polynomial evaluation algorithm, which reforms the evaluation process to include an increased num-ber of squaring steps. By using a squarer design that is more effcient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs 14

A scalable sparse matrix-vector multiplication kernel for en...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Dorrance, Richard Ren, Fengbo Marković, Dejan EE Department UCLA Los Angeles CA 90095 United States

ISBN: (纸本)9781450326711

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共65页 << < 23 24 25 26 27 28 29 30 31 32 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：