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A FPGA prototype design emphasis on low power technique 14

A FPGA prototype design emphasis on low power technique

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Hanyang, Xu Jian, Wang Jinmei, Lai Fudan University No.825 Zhangheng Rd shanghai China

ISBN: (纸本)9781450326711

In this paper, we propose a fully-functional Nanometer FPGA prototype chip. Compared to traditional single supply voltage, single threshold voltage design, we explore low power nanometer FPGA design challenges with Multi-Vt, Static Voltage Scaling and sleep mode technique. Compared to Dynamic Voltage Scaling (DVS), we make a table of Voltage-Delay parameter pairs under different voltage conditions so that timing information can be calculated by a Static Timing Analysis (STA) tool. Thus a lowest supply power is chosen among all results which meet the timing requirements. This approach would simplify the hardware design since we don't need a complex workload detection circuit compared to DVS system. By separating supply voltages, we can directly shutdown power supply of the unused circuits. Compared to inserting sleep transistor in pull-up or pull-down networks, we can eliminate the speed penalty cased by the additional sleep transistor. We implement a tile-based heterogeneous architecture with island style routing and embedded specific blocks such as DSP and memory. The array size is 6431 (RowCol) including 6424 CLBs. The final design is fabricated using a 1P10M 65-nm bulk CMOS process. Test results show a 53% reduction in static power compared to a commercial FPGA device which is also fabricated in 65nm process and has a similar array size.

关键词： field programmable gate arrays (FPGA)

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MPack: Global memory optimization for stream applications in high-level synthesis 14

MPack: Global memory optimization for stream applications in...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Vasiljevic, Jasmina Chow, Paul Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781450326711

One of the challenges in designing high-performance FPGA applications is fine-tuning the use of limited on-chip memory storage among many buffers in an application. To achieve desired performance the designer faces the burden of packaging such buffers into on-chip memories and manually optimizing the utilization of each memory and the throughput of each buffer. In addition, the application memories may not match the word width or depth of the physical on-chip memories available on the FPGA. This process is time consuming and non-trivial, particularly with a large number of buffers of various depths and bit widths. We propose a tool, MPack, which globally optimizes on-chip memory use across all buffers for stream applications. The goal is to speed up development time by providing rapid design space exploration and relieving the designer of lengthy low-level iterations. We introduce new high-level pragmas allowing the user to specify global memory requirements, such as an application's on-chip memory budget and data throughput. We allow the user to quickly generate a large number of memory solutions and explore the trade-off between memory usage and achievable throughput. To demonstrate the effectiveness of our tool, we apply the new high-level pragmas to an image processing benchmark. MPack effectively explores the design space and is able to produce a large number of memory solutions ranging from 10 to 100% in throughput, and from 12 to 100% in on-chip memory usage.

关键词： field programmable gate arrays (FPGA)

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CAD and routing architecture for interposer-based multi-FPGA systems 14

CAD and routing architecture for interposer-based multi-FPGA...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Pereira, Andre Hahn Betz, Vaughn Computer and Digital Systems Engineering Department-Escola Politécnica University of São Paulo São Paulo SP Brazil Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

Interposer-based multi-FPGA systems are composed of mul-tiple FPGA dice connected through a silicon interposer. Such devices allow larger FPGA systems to be built than one monolithic die can accomodate and are now commercially available. An open question, however, is how efficient such systems are compared to a monolithic FPGA, as the num-ber of signals passing between dice is reduced and the signal delay between dice is increased in an interposer system vs. a monolithic FPGA. We create a new version of VPR to investigate the archi-tecture of such systems, and show that by modifying the placement cost function to minimize the number of signals that must cross between dice we can reduce routing demand by 18% and delay by 2%. We also show that the signal count between dice and the signal delay between dice are key archi-tecture parameters for interposer-based FPGA systems. We find that if an interposer supplies (between dice) 60% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is little impact on the routability of circuits. Smaller routing capacities in the interposer do im-pact routability however: minimum channel width increases by 20% and 50% when an interposer supplies only 40% and 30% of the within-die routing, respectively. The interposer also impacts delay, increasing circuit delay by 34% on aver-age for a 1 ns interposer signal delay and a four-die system. Reducing the interposer delay has a greater benefit in im-proving circuit speed than does reducing the number of dice in the system.

关键词： field programmable gate arrays (FPGA)

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Towards interconnect-adaptive packing for FPGAs 14

Towards interconnect-adaptive packing for FPGAs

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Luu, Jason Rose, Jonathan Anderson, Jason Dept. Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

In order to investigate new FPGA logic blocks, FPGA ar-chitects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to cre-ate such CAD tools can be a time-consuming process that can significantly limit the number and variety of architec-tures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from im-practically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being in-vestigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common inter-connect structures that are used to create many kinds of use-ful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing , pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modi-fications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultane-ously expanding the scope of architectures that can be ex-plored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower crit-ical path delay. We obtain a 6 to 7-fold speedup for archi-tectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

关键词： field programmable gate arrays (FPGA)

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[email protected] all-programmable SoC ecosystem 14

[email protected] all-programmable SoC ecosystem

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Antonio Filgueras Eduard Gil Daniel Jimenez-Gonzalez Carlos Alvarez Xavier Martorell Jan Langer Juanjo Noguera Kees Vissers Barcelona Supercomputing Center - BSC-CNS Barcelona Spain Universitat Politecnica de Catalunya - UPC Barcelona Spain Xilinx Inc. Dublin Ireland Xilinx inc. San Jose CA USA

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： task dataflow models automatic hardware generation framework heterogenous parallel programming model

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Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a FPGA provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for FPGAs using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire FPGA based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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FPGA'11 - proceedings of the 2011 acm/sigda international symposium on field programmable gate arrays

FPGA'11 - Proceedings of the 2011 ACM/SIGDA International Sy...

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2011 19th acm/sigda international symposium on field programmable gate arrays, FPGA'11

ISBN: (纸本)9781450305549

The proceedings contain 37 papers. The topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: automatic memory and cache management for reconfigurable logic;NETTM: faster and easier synchronization for soft multicores via transactional memory;LegUp: high-level synthesis for FPGA-based processor/accelerator systems;automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs;Torc: towards an open-source tool flow;FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting;a platform for high level synthesis of memory-intensive image processing algorithms;energy-efficient specialization of functional units in a coarse-grained reconfigurable array;and DEEP: an iterative FPGA-based many-core emulation system for chip verification and architecture research.

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Improving bitstream compression by modifying FPGA architecture 13

Improving bitstream compression by modifying FPGA architectu...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Location, location, location - The role of spatial locality in asymptotic energy minimization 13

Location, location, location - The role of spatial locality ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： DeHon, André M. Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Locality exploitation is essential to asymptotic energy minimization for gate array netlist evaluation. Naive implementations that ignore locality, including flat crossbars and simple processors based on monolithic memories, can require O(N2) energy for an N node graph. Specifically, it is important to exploit locality (1) to reduce the size of the description of the graph, (2) to reduce data movement, and (3) to reduce instruction movement. FPGAs exploit all three. FPGAs with a Rent Exponent p © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Faithful single-precision floating-point tangent for FPGAs 13

Faithful single-precision floating-point tangent for FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre High Wycombe United Kingdom

ISBN: (纸本)9781450318877

This paper presents an FPGA-specific implementation of the floating-point tangent function. The implementation inputs values in the interval [-π/2,π/2], targets the IEEE-754 single-precision format and has an accuracy of 1 ulp. The proposed work is based on a combination of mathematical identities and properties of the tangent function in floating point. The architecture was designed having the {Stratix-IV} DSP and memory blocks in mind but should map well on any contemporary FPGA featuring embedded multiplier and memory blocks. It outperforms generic polynomial approximation targeting the same resource spectrum and provides better resources trade-offs than classical CORDIC-based *** presented work is widely available as being part of the Altera DSP Builder Advanced Blockset. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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