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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是401-410 订阅

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Armada: Timing-driven pipeline-aware routing for FPGAs

Armada: Timing-driven pipeline-aware routing for FPGAs

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Eguro, Ken Hauck, Scott Electrical Engineering Department University of Washington Seattle WA

ISBN: (纸本)1595932925

While previous research has shown that FPGAs can efficiently inclement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although there have been two heuristics developed to address this issue, both have certain limitations and neither approach considers timing during the routing process. While timing-driven conventional routing is largely considered to be a solved problem, there are several issues inherent to the N-Delay Routing problem make addressing timing particularly difficult, m this paper we discuss the nature of these problems and present a new timing-driven pipeline-aware router that produces as much as 60% better critical path delay than previous efforts. Copyright 2006 acm.

关键词： field programmable gate arrays

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Yield enhancements of design-specific FPGAs 06

Yield enhancements of design-specific FPGAs

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Campregher, Nicola Cheung, Peter Y. K. Constantinides, George A. Vasilko, Milan Electrical and Electronic Engineering Imperial College London United Kingdom School of Design Engineering and Computing Bournemouth University United Kingdom

ISBN: (纸本)1595932925

The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the development of Design-Specific FPGAs. These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific FPGAs. In this paper, an analytical model predicting the probability of mapping a specific design onto potentially defective FPGAs is developed. When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific FPGA approach is reported for current and future technology nodes. It is found that this approach, while beneficial with current manufacturing technology, may not be suitable for 22nm technology or beyond. Copyright 2006 acm.

关键词： field programmable gate arrays

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Measuring the gap between FPGAs and ASICs 06

Measuring the gap between FPGAs and ASICs

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Kuon, Ian Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto Ont. Canada

ISBN: (纸本)1595932925

This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flipflops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller. Copyright 2006 acm.

关键词： field programmable gate arrays

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Performance benefits of monolithically stacked 3D-FPGA 06

Performance benefits of monolithically stacked 3D-FPGA

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Lin, Mingjie Gamal, Abbas El Lu, Yi-Chang Wong, Simon Department of Electrical Engineering Stanford University CA 94305 United States

ISBN: (纸本)1595932925

The performance benefits of a monolithically stacked 3D-FPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-FPGA fabric is used as a baseline for quantifying the relative improvements in logic density, delay, and power consumption achieved by such a 3D-FPGA. It is assumed that only the pass-transistor switches and configuration memory cells can be moved to the top layers and that the 3D-FPGA employs the same logic block and programmable interconnect architecture as the baseline 2D-FPGA. Assuming a configuration memory cell that is ≤ 0.7 the area of an SRAM cell and pass-transistor switches having the same characteristics as nMOS devices in the CMOS layer are used, it is shown that a monolithically stacked 3D-FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2D-FPGA fabricated in the same 65nm technology node. Copyright 2006 acm.

关键词： field programmable gate arrays

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Power-aware RAM mapping for FPGA embedded memory blocks 06

Power-aware RAM mapping for FPGA embedded memory blocks

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Tessier, Russell Betz, Vaughn Neto, David Gopalsamy, Thiagaraja Department of Electrical and Computer Engineering University of Massachusetts Amherst MA United States Altera Toronto Technology Centre 151 Bloor St Toronto Ont. Canada Altera Corporation 101 Innovation Drive San Jose CA United States

ISBN: (纸本)1595932925

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance. Copyright 2006 acm.

关键词： field programmable gate arrays

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Design of a Single Event Upset (SEU) mitigation technique for programmable devices 06

Design of a Single Event Upset (SEU) mitigation technique fo...

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7th international symposium on Quality Electronic Design

作者： Baloch, S. Arslan, T. Stoica, A. Alba Centre Inst Syst Level Integrat Alba Campus Livingston EH54 7EG Scotland Univ Edinburgh Sch Elect & Engg Edinburgh EH8 9YL Midlothian Scotland NASA Jet Propuls Lab Pasadena CA 91109 USA

ISBN: (纸本)0769525237

This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.

关键词： Single event upset field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation programmable logic arrays Latches

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Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs 06

Analysis and experimental results of an FPGA-based strategy ...

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7th international symposium on Quality Electronic Design

作者： De Venuto, Daniela Reyneri, Leonardo Politecn Bari Bari Italy Politecn Torino Turin Italy

ISBN: (纸本)0769525237

This work describes an intensive investigation on the test strategy known as polynomial fitting that uses FPGA generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. The proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.

关键词： Production Circuit testing Automatic testing Polynomials Built-in self-test Signal generators Linearity Histograms Performance evaluation field programmable gate arrays

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Probabilistic delay budgeting for soft realtime applications 06

Probabilistic delay budgeting for soft realtime applications

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7th international symposium on Quality Electronic Design

作者： Ghiasi, Soheil Huan, Po-Kuan Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769525237

Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. This paradigm shaft calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multimedia applications on FPGAs show about 20% and 19% average energy and area improvement, respectively.

关键词： Timing Delay effects Hardware Flow graphs Application software Algorithm design and analysis Data flow computing Design methodology Stochastic processes field programmable gate arrays

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Dual-Vt design of FPGAs for subthreshold leakage tolerance 06

Dual-Vt design of FPGAs for subthreshold leakage tolerance

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7th international symposium on Quality Electronic Design

作者： Kumar, Akhilesh Anis, Mohab Univ Waterloo Dept ECE 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769525237

In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures.

关键词： field programmable gate arrays Subthreshold current Routing Switches Design automation Circuits Threshold voltage Logic design Sleep MOS devices

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