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programmable memory blocks supporting content-addressable memory 00

Programmable memory blocks supporting content-addressable me...

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Heile, Frank Leaver, Andrew Veenstra, Kerry Altera San Jose CA United States

ISBN: (纸本)9781581131932

The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as well as product term macrocells, ROM, and dual port RAM. In CAM mode each ESB can implement a 32 word CAM with 32 bits per word. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiting creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.

关键词： Logic devices

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Novel high throughput reconfigurable FPGA architecture

Novel high throughput reconfigurable FPGA architecture

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Singh, Amit Macchiarulo, Luca Mukherjee, Arindam Marek-Sadowska, Malgorzata Univ of California Santa Barbara Santa Barbara United States

With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. This architecture utilizes the concept of `Wave-Steering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5 μ CMOS technology.

关键词： field programmable gate arrays

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FPGA implementation and performance evaluation of the Serpent block cipher

FPGA implementation and performance evaluation of the Serpen...

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Elbirt, A.J. Paar, C. Worcester Polytechnic Inst Worcester MA United States

With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as field programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an FPGA implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current FPGAs.

关键词： field programmable gate arrays

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Synthesis for FPGAs with embedded memory blocks 00

Synthesis for FPGAs with embedded memory blocks

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Cong, Jason Yan, Kenneth Univ of California Los Angeles CA United States

ISBN: (纸本)9781581131932

Embedded memory blocks (EMBs) are used in modern field programmable gate arrays (FPGAs) for implementation of on-chip memories or specialized logic functions. In this paper, we propose an integrated approach with structural clustering and functional decomposition to minimize the circuit area using EMBs while preserving the circuit delay. The structural clustering method is based on the concepts of Maximum Fanout Free Cone (MFFC) and Maximum Fanout Free Subgraph (MFFS). In order to effectively use EMB in large clusters, single-output and multiple-output functional decompositions are used to decompose large clusters so that the encoding functions or base functions can be implemented by EMBs. It also considers multiple EMBs for individual large cluster so that better area reduction can be obtained. We have developed an algorithm called EMB_Syn that can be used as a postprocessing tool in the FPGA synthesis flow. MCNC benchmarks are used to test EMB_Syn on Altera's FLEX10K device family and the experimental results are compared with those by EMB_Pack and SMAP. When EMB_Syn is used as postmapping processing, it shows 45.06% and up to 5.23% improvements over EMB_Pack and SMAP, respectively, in terms of the covered area by EMBs.

关键词： field programmable gate arrays

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Timing-driven placement for FPGAs 00

Timing-driven placement for FPGAs

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Marquardt, Alexander Betz, Vaughn Rose, Jonathan Right Track CAD Corp Toronto Ont Canada

ISBN: (纸本)9781581131932

In this paper we introduce a new Simulated Annealing-based timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a novel method of determining source-sink connection delays during placement. Second, we introduce a new cost function that trades off between wire-use and critical path delay, resulting in significant reductions in critical path delay without significant increases in wire-use. Finally, we combine connection-based and path-based timing-analysis to obtain an algorithm that has the low time-complexity of connection-based timing-driven placement, while obtaining the quality of path-based timing-driven placement. A comparison of our new algorithm to a well known non-timing-driven placement algorithm demonstrates that our algorithm is able to increase the post-place-and-route speed (using a full path-based timing-driven router and a realistic routing architecture) of 20 MCNC benchmark circuits by an average of 42%, while only increasing the minimum wiring requirements by an average of 5%.

关键词： field programmable gate arrays

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Technology mapping for k/m-macrocell based FPGAs 00

Technology mapping for k/m-macrocell based FPGAs

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Cong, Jason Huang, Hui Yuan, Xin Univ of California Los Angeles CA United States

ISBN: (纸本)9781581131932

In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experiment results show our algorithm can achieve depth-optimality in practically all cases. Furthermore it is shown that the k/m-macrocell based FPGAs are practically equivalent to the traditional k-LUT based FPGAs with only a relatively small number of product terms (m≤k+3). We also investigate the total area and delay of k/m-macrocell based FPGAs on various benchmarks to compare it with commonly used 4-LUT based FPGAs. The experimental result shows k/m-macrocell based FPGAs can outperform 4-LUT based FPGAs in terms of both delay and area after placement and routing by VPR.

关键词： field programmable gate arrays

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Representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

Representation for dynamic graphs in reconfigurable hardware...

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Huelsbergen, Lorenz Bell Lab Murray Hill United States

This paper gives a representation for graph data structures as electronic circuits in reconfigurable hardware. Graph properties, such as vertex reachability, are computed quickly by exploiting a graph's edge parallelism - signals propagate along many graph edges concurrently. This new representation admits arbitrary graphs in which vertices/edges may be inserted and deleted dynamically at low cost - graph modification does not entail any re-fitting of the graph's circuit. Dynamic modification is achieved by rewriting cells in a re-configurable hardware array. Dynamic graph algorithms are given for vertex reachability, transitive closure, shortest unit path, cycle detection, and connected-component identification. On the task of computing a graph's transitive closure, for example, simulation of such a dynamic graph processor indicates possible speedups greater than three orders of magnitude compared to an efficient software algorithm running on a contemporaneously fast uniprocessor. Implementation of a prototype in an FPGA verifies the accuracy of the simulation and demonstrates that a practical and efficient (compact) mapping of the graph construction is possible in existing FPGA architectures. In addition to speeding conventional graph computations with dynamic graph processors, we note their potential as parallel graph reducers implementing general (Turing equivalent) computation.

关键词： field programmable gate arrays

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Generating highly-routable sparse crossbars for PLDs 00

Generating highly-routable sparse crossbars for PLDs

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Lemieux, Guy Leventis, Paul Lewis, David Univ of Toronto Toronto Ont Canada

ISBN: (纸本)9781581131932

A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to accurately compute the percentage of random test vectors that can be routed. The construction method attempts to maximize the spread of the switch locations, such that any given subset of input wires can connect to as many output wires as possible. Based on Hall's Theorem, we argue that this increases the likelihood of routing. The hardest test vectors to route are those which attempt to use all of the crossbar outputs. Results in this paper show that area-efficient sparse crossbars can be constructed by providing more outputs than required and a sufficient number of switches. In a few specific case studies, it is shown that sparse crossbars with about 90% fewer switches than a full crossbar can be constructed, and these crossbars are capable of routing over 95% of randomly chosen routing vectors. In one case, a new switch matrix which can replace the one in the Altera FLEX8000 family is shown. This new switch matrix uses approximately 14% more transistors, yet can increase the routability of the most difficult test vectors from 1% to over 96%.

关键词： field programmable gate arrays

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Tolerating operational faults in cluster-based FPGAs 00

Tolerating operational faults in cluster-based FPGAs

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Lakamraju, Vijay Tessier, Russell Univ of Massachusetts Amherst MA United States

ISBN: (纸本)9781581131932

In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults. Our preferred approach to fault recovery takes advantage of device routing hierarchy in architectural families such as Xilinx Virtex and Altera Apex to quickly swap unused logic and routing resources in place of faulty ones within logic clusters. These algorithms allow for straightforward implementation within a local fault-tolerant system without the need to access a remote processing location. If initial recovery attempts through localized swapping fail, an incremental router based on the widely-used PathFinder maze routing algorithm can be applied remotely in an attempt to form connections between newly-allocated logic and interconnect based on the history of the initial design route.

关键词： field programmable gate arrays

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Factoring large numbers with programmable hardware 00

Factoring large numbers with programmable hardware

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FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Kim, Hea Joung Mangione-Smith, William H. Univ of California Los Angeles CA United States

ISBN: (纸本)9781581131932

Most advanced forms of security for electronic transactions rely on the public-key cryptosystems developed by Rivest, Shamir and Adleman. Unfortunately, these systems are only secure while it remains difficult to factor large integers. The fastest published algorithms for factoring large numbers have a common sieving step. These sieves collect numbers that are completely factored by a set of prime numbers that are known in advance. Furthermore, the time required to execute these sieves currently dominates the runtime of the factoring algorithms. We show how the sieving process can be mapped to the Mojave configurable computing architecture. The mapping exploits unique properties of the sieving algorithms to fully utilize the bandwidth of a multiple bank interleaved memory system. The sieve has been mapped to a single programmable hardware unit on the Mojave computer, and achieves a clock frequency of 16 MHz. The full system implementation sieves over 28 times faster than an UltraSPARC Workstation. A simple upgrade to 8 ns SRAMs will result in a speedup factor of 160.

关键词： Cryptography

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