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检索条件"任意字段=Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 642 条记录，以下是81-90 订阅

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FPGA 2015 - 2015 acm/sigda international symposium on field-programmable gate arrays

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

ISBN: (纸本)9781450333153

The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point FPGAs;software-driven hardware development;InTime: a machine learning approach for efficient selection of FPGA CAD tool parameters;enhancing hardware design flows with MyHDL;rapid prototyping of wireless physical layer modules using flexible software/hardware design flow;application of specific delay window routing for timing optimization in FPGA designs;application of specific delay window routing for timing optimization in FPGA designs;fine-grained interconnect synthesis;delay-bounded routing for shadow registers;EURECA: on-chip configuration generation for effective dynamic data access;energy-efficient discrete signal processing with field programmable analog arrays (FPAAs);expanding OpenFlow capabilities with virtualized reconfigurable hardware.

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High Density Pipelined 8bit Multiplier Systolic arrays for FPGA 20

High Density Pipelined 8bit Multiplier Systolic Arrays for F...

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proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Martin Langhammer Sergey Gribok Gregg Baeckler Intel Marlow United Kingdom Intel San Jose CA USA

ISBN: (纸本)9781450370998

With the advent of AI and machine learning as the highest profile FPGA applications, INT8 performance is currently one of the key benchmarking metrics. In current devices, INT8 multipliers must be extracted from higher precision multipliers. Recently, we reported the implementation of a mixed DSP Block and soft logic design, with 22,400 INT8 multipliers, and a system clock rate of 416MHz, on the Intel Stratix 10 2800 *** this paper we demonstrate alternate techniques for integer multiplier construction to better balance the resource types on current FPGAs - logic, memory, and DSP - to make a significant improvement in the multiplier, and therefore the dot product, density. We further extend these techniques to 8 bit signed-magnitude (SM) 1.7 representation, which can further improve arithmetic density by using the logic and memory resources more flexibly. We describe variable composition dot product structures, which can be assembled in a scalable 2D systolic array. In one example, we report a design containing 32,768 SM1.7 multipliers, with a clock rate of 432MHz, giving a system performance of over 28 TOPs. Our INT8 densities are improved by up to 30% over the earlier work - we show one design with 28,800 INT8 multipliers. In all cases, enough device resources are left free and accessible to implement a full application level design.

关键词： int8 array fpga multiplier

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High-Performance QR Decomposition for FPGAs 18

High-Performance QR Decomposition for FPGAs

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Langhammer, Martin Pasca, Bogdan Intel Programmable Solut Grp Swindon Wilts England Intel Programmable Solut Grp Paris France

ISBN: (纸本)9781450356145

QR decomposition (QRD) is of increasing importance for many current applications, such as wireless and radar. Data dependencies in known algorithms and approaches, combined with the data access patterns used in many of these methods, restrict the achievable performance in software programmable targets. Some FPGA architectures now incorporate hard floating-point (HFP) resources, and in combination with distributed memories, as well as the flexibility of internal connectivity, can support high-performance matrix arithmetic. In this work, we present the mapping to parallel structures with inter-vector connectivity of a new QRD algorithm. Based on a Modified Gram-Schmidt (MGS) algorithm, this new algorithm has a different loop organization, but the dependent functional sequences are unchanged, so error analysis and numerical stability are unaffected. This work has a theoretical sustained-to-peak performance close to 100% for large matrices, which is roughly three times the functional density of the previously best known implementations. Mapped to an Intel Arria 10 device, we achieve 80us for a 256x256 single precision real matrix, for a 417 GFLOP equivalent. This corresponds to a 95% sustained to peak ratio, for the portion of the device used for this work.

关键词： QRD MGS FPGA Arria10 throughput

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Architecture Exploration for HLS-Oriented FPGA Debug Overlays 18

Architecture Exploration for HLS-Oriented FPGA Debug Overlay...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Jamal, Al-Shahna Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada Brigham Young Univ Provo UT 84602 USA

ISBN: (纸本)9781450356145

High-Level Synthesis (HLS) promises improved designer productivity, but requires a debug ecosystem that allows designers to debug in the context of the original source code. Recent work has presented in-system debug frameworks where instrumentation added to the design collects trace data as the circuit runs, and a software tool that allows the user to replay the execution using the captured data. When searching for the root cause of a bug, the designer may need to modify the instrumentation to collect data from a new part of the design, requiring a lengthy recompile. In this paper, we propose a flexible debug overlay family that provides software-like debug turn-around times for HLS generated circuits. At compile time, the overlay is added to the design and compiled. At debug time, the overlay can be configured many times to implement specific debug scenarios without a recompilation. This paper first outlines a number of "capabilities" that such an overlay should have, and then describes architectural support for each of these capabilities. The cheapest overlay variant allows selective variable tracing with only a 1.7% increase in area overhead from the baseline debug instrumentation, while the deluxe variant offers 2x-7x improvement in trace buffer memory utilization with conditional buffer freeze support.

关键词： field-programmable gate Array Debugging High-Level Synthesis

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P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs 18

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s S...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： da Silva, Jeferson Santiago Boyer, Francois-Raymond Langlois, J. M. Pierre Polytech Montreal Montreal PQ Canada

ISBN: (纸本)9781450356145

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing languages with FPGAs seems to be the perfect match for these requirements. In this work, we develop an open-source FPGA-based configurable architecture for arbitrary packet parsing to be used in SDN networks. We generate low latency and high-speed streaming packet parsers directly from a packet processing program. Our architecture is pipelined and entirely modeled using templated C++ classes. The pipeline layout is derived from a parser graph that corresponds to a P4 code after a series of graph transformation rounds. The RTL code is generated from the C++ description using Xilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves a 100 Gb/s data rate in a Xilinx Virtex-7 FPGA while reducing the latency by 45% and the LUT usage by 40% compared to the state-of-the-art.

关键词： FPGA packet parsers HLS programmable networks P4

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Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software programmable FPGAs 18

Rosetta: A Realistic High-Level Synthesis Benchmark Suite fo...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Zhou, Yuan Gupta, Udit Dai, Steve Zhao, Ritchie Srivastava, Nitish Jin, Hanchen Featherston, Joseph Lai, Yi-Hsiang Liu, Gai Velasquez, Gustavo Angarita Wang, Wenping Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Harvard Univ Comp Sci Cambridge MA 02138 USA Univ Nacl Colombia Syst Engn & Comp Sci Bogota Colombia Zhejiang Univ Elect & Informat Engn Hangzhou Peoples R China

ISBN: (纸本)9781450356145

Modern high-level synthesis (HLS) tools greatly reduce the turnaround time of designing and implementing complex FPGA-based accelerators. They also expose various optimization opportunities, which cannot be easily explored at the register-transfer level. With the increasing adoption of the HLS design methodology and continued advances of synthesis optimization, there is a growing need for realistic benchmarks to (1) facilitate comparisons between tools, (2) evaluate and stress-test new synthesis techniques, and (3) establish meaningful performance baselines to track progress of the HLS technology. While several HLS benchmark suites already exist, they are primarily comprised of small textbook-style function kernels, instead of complete and complex applications. To address this limitation, we introduce Rosetta, a realistic benchmark suite for software programmable FPGAs. Designs in Rosetta are fully-developed applications. They are associated with realistic performance constraints, and optimized with advanced features of modern HLS tools. We believe that Rosetta is not only useful for the HLS research community, but can also serve as a set of design tutorials for non-expert HLS users. In this paper we describe the characteristics of our benchmarks and the optimization techniques applied to them. We further report experimental results on an embedded FPGA device as well as a cloud FPGA platform.

关键词： high-level synthesis fpga heterogeneous computing reconfigurable computing benchmarking

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Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA 29

Towards Trainable Synthesis for Optimized Circuit Deployment...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Legault, Jean-Philippe Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick FrederictonNB Canada Department of Computer Science University of Waikato Hamilton Waikato New Zealand

ISBN: (纸本)9781538675571

field programmable gate arrays (FPGAs) utilize multiple programmable elements and non-programmable blocks. After synthesizing an input Hardware Design Language (HDL) design into a circuit, optimizations are used to discover a satisfactory deployment on a target FPGA. HDLs' compound operations, such as addition, can be implemented in various ways and thus, multiple but functionally equivalent circuits can be synthesized. To leverage this, we propose a methodology that first enables configurable synthesis of compound operations. Second, it trains the system using a set of HDL files and architectures to optimize target performance objectives, such as critical path length and power. We prototyped our technique in the open source Verilog-To-Routing (VTR) tool. We subsequently produced two configuration files targeting different deployment objectives;experimental results with the VTR Verilog benchmarks revealed significant improvements. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Sparse Winograd Convolutional Neural Networks on Small-scale Systolic arrays 19

Sparse Winograd Convolutional Neural Networks on Small-scale...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Feng Shi Haochen Li Yuhe Gao Benjamin Kuschner Song-Chun Zhu University of California Los Angeles Los Angeles CA USA University of Hong Kong Hong Kong China

ISBN: (纸本)9781450361378

The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement a framework on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored recursive Z-Morton memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on various CNN models show that it achieves very high computation resource utilization, 20x~30x energy efficiency, and more than 5x speedup compared with the dense implementation.

关键词： systolic arrays convolutional neural networks sparse matrix multiplication fpga winograd transform

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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity 19

Embracing Systolic: Super Systolization of Large-Scale Circu...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Jiafeng Xie Chiou-Yng Lee Villanova University Villanova PA USA Lunghwa University of Science and Technology Taoyuan Taiwan Roc

ISBN: (纸本)9781450361378

The recent advance in artificial intelligence (AI) technology has led to a new round of systolic structure innovation. Many AI accelerators have employed systolic structure to realize the core large-scale matrix-vector multiplication for high-performance processing, which has a complexity of $o(n^2)$ for matrix size of $n\times n$ (difficult to be implemented on the field-programmable gate array (FPGA) platform). To overcome this drawback, in this paper, we propose a super systolization strategy to implement the core circulant matrix-vector multiplication into a systolic structure with subquadratic space complexity. The proposed effort is carried out through two stages of coherent interdependent efforts: (i) a novel matrix-vector multiplication algorithm based on Toeplitz matrix-vector product (TMVP) approach is proposed to obtain subquadratic space complexity; (ii) a series of optimization techniques are introduced to map the proposed algorithm into desired systolic structure. Finally, detailed complexity analysis and comparison have been conducted to prove the efficiency of the proposed strategy. The proposed strategy is highly efficient and can be extended in many neural network based hardware implementation platforms.

关键词： field-programmable gate array systolic structure large-scale toeplitz matrix vector product circulant matrix-vector multiplication subquadratic space complexity

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Message-Oriented Devices on FPGAs 29

Message-Oriented Devices on FPGAs

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Baumela, Thomas Gruber, Olivier Muller, Olivier Pétrot, Frédéric Univ. Grenoble Alpes CNRS Grenoble Institute of Engineering TIMA Grenoble38000 France

ISBN: (纸本)9781538675571

Embedded systems increasingly include an FPGA for performance or power efficiency. Fortunately, FPGA makers provide efficient tools to develop and assemble multiple Intellectual Properties (IPs) as devices on FPGAs. Unfortunately, the integration challenge does not stop there, hardware devices are only usable if they have available software device drivers executing on the processor subsystem. To better approach this end-to-end integration challenge, across both hardware and software, we argue that both sides need to evolve. We propose to take a step towards message-based interfaces for hardware devices integrated on an FPGA. Our goal is to deliver to the FPGA market the plug-and-play value of the USB stack with essentially no performance overhead, negligible power increase, and a reasonable surface cost. We have implemented our proposal on the Xilinx Zynq SoC, combining ARM cores and an FPGA, demonstrating the feasibility of the approach. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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