检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

577 篇 会议
31 篇 期刊文献

馆藏范围

608 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

521 篇 工学
- 469 篇 计算机科学与技术...
- 289 篇 软件工程
- 227 篇 电子科学与技术（可...
- 157 篇 电气工程
- 86 篇 信息与通信工程
- 36 篇 控制科学与工程
- 35 篇 动力工程及工程热...
- 23 篇 机械工程
- 14 篇 生物工程
- 12 篇 仪器科学与技术
- 10 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 5 篇 材料科学与工程（可...
- 3 篇 农业工程
201 篇 理学
- 166 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 15 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
57 篇 管理学
- 48 篇 管理科学与工程(可...
- 30 篇 工商管理
- 10 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学
1 篇 医学

主题

261 篇 field programmab...
173 篇 field programmab...
39 篇 clocks
35 篇 signal processin...
34 篇 estimation
34 篇 filtration
33 篇 modulation
33 篇 ofdm
31 篇 fpga
8 篇 field-programmab...
7 篇 fpgas
7 篇 computer archite...
7 篇 systolic arrays
7 篇 optimization
7 篇 high-level synth...
7 篇 field-programmab...
7 篇 reconfigurable c...
6 篇 hardware
6 篇 field programmab...
5 篇 routing

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 univ british col...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university
3 篇 state key lab of...

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 pasca bogdan
7 篇 constantinides g...
7 篇 chow paul
6 篇 wilton steven j....
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

601 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 608 条记录，以下是91-100 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Self-decompressing FPGA Bitstreams 62

Self-decompressing FPGA Bitstreams

引用

62nd IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Ma, Shenghou Ampadu, Paul Virginia Tech ECE Dept Blacksburg VA 24061 USA

ISBN: (纸本)9781728127880

SRAM based FPGAs (field programmable gate arrays) are volatile devices, and need to reload its configuration (bitstream) every time after power up. Bitstream compression is one of the major method to reduce the cost of storing the configuration storage and speed up configuration. However, existing complete bitstream (as compared to partial bitstream) compression methods require an external decompresser implemented either in another FPGA or CPU. This drawback prevents deployment of bitstream compression to already in-field systems. This paper drew inspiration from self-extracting archive, and utilizes the self partial reconfiguration capabilities of modern FPGAs to create a self-decompressing FPGA bitstreams so that the decompression engine is located inside the compressed bitstream itself. Analysis showed that this method will never increase the size of bitstream, and can achieve configuration time reduction whenever the compression ratio is smaller than 7/9 and the configuration reduction scales almost linearly with the compression ratio. Furthermore, the paper shows that by using bitstream assembly techniques, it is possible to choose the compression algorithm after building the target bitstream, therefore, the best compression ratio can be achieved given a pool of available decompression engines.

关键词： field programmable gate arrays configuration compression decompression hardware reconfigurable logic configuration datastreams

来源：评论

学校读者我要写书评

暂无评论

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA 32

Criticality Aware Soft Error Mitigation in the Configuration...

引用

32nd international Conference on VLSI Design (VLSID) / 18th international Conference on Embedded Systems (ES)

作者： Mandal, Swagata Sarkar, Sreetama Ming, Wong Ming Chattopadhyay, Anupam Chakrabarti, Amlan Nanyang Technol Univ Singapore Singapore Univ Calcutta Kolkata India

ISBN: (纸本)9781728104096

Efficient low complexity error correcting code (ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory (CM) of static random access memory (SRAM) based field programmable gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper, we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliability.

关键词： Task analysis field programmable gate arrays Error correction codes Random access memory Product codes Hardware Error correction

来源：评论

学校读者我要写书评

暂无评论

FPGA 2015 - 2015 acm/sigda international symposium on field-programmable gate arrays

FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

ISBN: (纸本)9781450333153

The proceedings contain 35 papers. The topics discussed include: using source-level transformations to improve high-level synthesis debug and validation on fpgas;high-level design tools for floating point FPGAs;software-driven hardware development;InTime: a machine learning approach for efficient selection of FPGA CAD tool parameters;enhancing hardware design flows with MyHDL;rapid prototyping of wireless physical layer modules using flexible software/hardware design flow;application of specific delay window routing for timing optimization in FPGA designs;application of specific delay window routing for timing optimization in FPGA designs;fine-grained interconnect synthesis;delay-bounded routing for shadow registers;EURECA: on-chip configuration generation for effective dynamic data access;energy-efficient discrete signal processing with field programmable analog arrays (FPAAs);expanding OpenFlow capabilities with virtualized reconfigurable hardware.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Accelerating Deterministic and Stochastic Binarized Neural Networks on FPGAs Using OpenCL 62

Accelerating Deterministic and Stochastic Binarized Neural N...

引用

62nd IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Lammie, Corey Xiang, Wei Azghadi, Mostafa Rahimi James Cook Univ Coll Sci & Engn Townsville Qld 4814 Australia

ISBN: (纸本)9781728127880

Recent technological advances have proliferated the available computing power, memory, and speed of modern Central Processing Units (CPUs), Graphics Processing Units (GPUs), and field programmable gate arrays (FPGAs). Consequently, the performance and complexity of Artificial Neural Networks (ANNs) is burgeoning. While GPU-accelerated Deep Neural Networks (DNNs) currently offer state-of-the-art performance, they consume large amounts of power. Training such networks on CPUs is inefficient, as data throughput and parallel computation is limited. FPGAs are considered a suitable candidate for performance critical, low power systems, e.g. the Internet of Things (IOT) edge devices. Using the Xilinx SDAccel or Intel FPGA SDK for OpenCL development environment, networks described using the high-level OpenCL framework can be accelerated on heterogeneous platforms. Moreover, the resource utilization and power consumption of DNNs can be further enhanced by utilizing regularization techniques that binarize network weights. In this paper, we introduce, to the best of our knowledge, the first FPGA-accelerated stochastically binarized DNN implementations, and compare them to implementations accelerated on both GPUs and FPGAs. All our developed networks are trained and benchmarked using the popular MNIST and CIFAR-10 datasets. For our binarized and conventional FPGA-based networks, we achieve a >16-fold improvement in power consumption, compared to their GPU-accelerated counterparts. Also, our binarized FPGA-based networks require >25% shorter inference times, compared to their GPU-based counterparts.

关键词： field programmable gate arrays Acceleration Graphics processing units Training Kernel Neural networks Computer architecture

来源：评论

学校读者我要写书评

暂无评论

High Performance Heterogeneous Multicore Architectures: A Study 3

High Performance Heterogeneous Multicore Architectures: A St...

引用

3rd international symposium on Computer Science and Intelligent Control, ISCSIC 2019

作者： Hoxha, Igla Agyeman, Michael Opoku University of Northampton Northampton United Kingdom

ISBN: (纸本)9781450376617

The significant increase in the need for high-performance and energy-efficient computing systems has introduced heterogenous computing. However, the incorporation of different architectures into one system complicates the distribution of the workload between architectures. To address this challenge while meeting the goals of high-performance computing systems, several research contributions have been made. This paper reviews some of the proposed workload partitioning approaches for GPU-based, DSP-based and FPGA-based heterogenous systems. This research also covers some comparison studies regarding the FPGA versus DSP and FPGA versus GPU debates, showing that sometimes collaboration between these architectures seems to be the key. The aim of this study is to provide academic and industrial researchers with an insight of techniques to achieve the workload balancing in heterogenous systems and motivate them for further research in the field. © 2019 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder 62

Effectively Partitioned Implementation for Successive-Cancel...

引用

62nd IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： Ideguchi, Yuta Kamiya, Norifumi Tawada, Masashi Togawa, Nozomu NEC Corp Ltd Tokyo Japan Waseda Univ Tokyo Japan

ISBN: (纸本)9781728127880

This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N-1/N-2) can be divided into two parts: N-1 SC decoders of length N-2 and a single SC decoder of length N-1. While the N-1 decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N-1 of N, and we show that an appropriate choice of N-1 yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.

关键词： Decoding Clocks field programmable gate arrays Hardware Throughput Computer architecture

来源：评论

学校读者我要写书评

暂无评论

High Density Pipelined 8bit Multiplier Systolic arrays for FPGA 20

High Density Pipelined 8bit Multiplier Systolic Arrays for F...

引用

proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Martin Langhammer Sergey Gribok Gregg Baeckler Intel Marlow United Kingdom Intel San Jose CA USA

ISBN: (纸本)9781450370998

With the advent of AI and machine learning as the highest profile FPGA applications, INT8 performance is currently one of the key benchmarking metrics. In current devices, INT8 multipliers must be extracted from higher precision multipliers. Recently, we reported the implementation of a mixed DSP Block and soft logic design, with 22,400 INT8 multipliers, and a system clock rate of 416MHz, on the Intel Stratix 10 2800 *** this paper we demonstrate alternate techniques for integer multiplier construction to better balance the resource types on current FPGAs - logic, memory, and DSP - to make a significant improvement in the multiplier, and therefore the dot product, density. We further extend these techniques to 8 bit signed-magnitude (SM) 1.7 representation, which can further improve arithmetic density by using the logic and memory resources more flexibly. We describe variable composition dot product structures, which can be assembled in a scalable 2D systolic array. In one example, we report a design containing 32,768 SM1.7 multipliers, with a clock rate of 432MHz, giving a system performance of over 28 TOPs. Our INT8 densities are improved by up to 30% over the earlier work - we show one design with 28,800 INT8 multipliers. In all cases, enough device resources are left free and accessible to implement a full application level design.

关键词： int8 array fpga multiplier

来源：评论

学校读者我要写书评

暂无评论

The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW 2019

The Evaluation of Partial Reconfiguration for a Multi-board ...

引用

10th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Yamakura, Miho Hironaka, Kazuei Azegami, Keita Musha, Kazusa Amano, Hideharu Keio Univ Yokohama Kanagawa Japan

ISBN: (纸本)9781450372558

FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected withflexible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Performance Evaluation of Tsunami Simulation Exploiting Temporal Parallelism on FPGAs using OpenCL 2019

Performance Evaluation of Tsunami Simulation Exploiting Temp...

引用

10th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Kono, Fumiya Nakasato, Naohito Kobe Univ Chuo Ku Kobe Hyogo 6500047 Japan Univ Aizu Ikki Machi Tsuruga Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781450372558

We developed and evaluated tsunami simulations on FPGAs by designing optimized OpenCL kernels that execute 2-D stencil calculation. By using Intel FPGA SDK for OpenCL, we obtained efficient FPGA designs exploiting temporal parallelism. The performance of our optimal implementation is 446 and 790 GFlops for Arria10 and Stratix10, respectively. These implementations are much faster than a design only exploiting spatial parallelism. The performance on Stratix10 is faster than our GPU implementation on Tesla V100 GPU.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

VIP: A Versatile Inference Processor 25

VIP: A Versatile Inference Processor

引用

25th IEEE international symposium on High Performance Computer Architecture (HPCA)

作者： Hurkat, Skand Martinez, Jose F. Microsoft Redmond WA 98052 USA Cornell Univ Ithaca NY USA

ISBN: (纸本)9781728114446

We present Versatile Inference Processor (VIP), a highly programmable architecture for machine learning inference. VIP consists of 128 lightweight processing engines employing a vector processing paradigm, with a simple ISA and carefully chosen microarchitecture features. It is coupled with a modern, lightly customized, 3D-stacked memory system. Through detailed execution-driven simulations backed by RTL synthesis, we show that we can achieve online, real-time vision throughput (24 fps), at low power consumption, for both full-HD depth-from-stereo using belief propagation, and VGG-16 and VGG-19 deep neural networks (batch size of 1). Our RTL synthesis of a VIP processing engine in TSMC 28nm technology, using a commercial standard-cell library supplied by ARM, results in 18mm(2) of silicon area and 3.5W to 4.8W of power consumption for all 128 VIP processing engines combined.

关键词： Engines Optical imaging field programmable gate arrays Convolution Task analysis Computer architecture Microarchitecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共61页 << < 6 7 8 9 10 11 12 13 14 15 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：