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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? 17

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neu...

引用

acm/sigda international symposium on field-programmable gate arrays

作者： Nurvitadhi, Eriko Venkatesh, Ganesh Sim, Jaewoong Marr, Debbie Huang, Randy Ong, Jason Gee Hock Liew, Yeong Tat Srivatsan, Krishnan Moss, Duncan Subhaschandra, Suchit Boudoukh, Guy Intel Corp Accelerator Architecture Lab Santa Clara CA 95051 USA Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Intel Corp FPGA Prod Team Santa Clara CA 95051 USA Intel Corp Comp Vis Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781450343541

Current-generation Deep Neural Networks (DNNs), such as AlexNet and VGG, rely heavily on dense floating-point matrix multiplication (GEMM), which maps well to GPUs (regular parallelism, high TFLOP/s). Because of this, GPUs are widely used for accelerating DNNs. Current FPGAs offer superior energy efficiency (Ops/Watt), but they do not offer the performance of today's GPUs on DNNs. In this paper, we look at upcoming FPGA technology advances, the rapid pace of innovation in DNN algorithms, and consider whether future high-performance FPGAs will outperform GPUs for next-generation DNNs. The upcoming Intel (R) 14-nm Stratix (TM) 10 FPGAs will have thousands of hard floating-point units (DSPs) and on-chip RAMs (M20K memory blocks). They will also have high bandwidth memories (HBMs) and improved frequency (HyperFlex (TM) core architecture). This combination of features brings FPGA raw floating point performance within striking distance of GPUs. Meanwhile, DNNs are quickly evolving. For example, recent innovations that exploit sparsity (e.g., pruning) and compact data types (e.g., 1-2 bit) result in major leaps in algorithmic efficiency. However, these innovations introduce irregular parallelism on custom data types, which are difficult for GPUs to handle but would be a great fit for FPGA's extreme customizability. This paper evaluates a selection of emerging DNN algorithms on two generations of Intel FPGAs (Arria (TM) 10, Stratix (TM) 10) against the latest highest performance Titan X Pascal GPU. We created a customizable DNN accelerator template for FPGAs and used it in our evaluations. First, we study various GEMM operations for next-generation DNNs. Our results show that Stratix 10 FPGA is 10%, 50%, and 5.4x better in performance (TOP/sec) than Titan X Pascal GPU on GEMM operations for pruned, Int6, and binarized DNNs, respectively. Then, we present a detailed case study on accelerating Ternary ResNet which relies on sparse GEMM on 2-bit weights (i.e., weights constrai

关键词： Deep Learning Accelerator Intel Stratix 10 FPGA GPU

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A Low-power APUF-based Environmental Abnormality Detection Framework 22

A Low-power APUF-based Environmental Abnormality Detection F...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Gu, Hongxiang Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Comp Sci Dept Los Angeles CA 90095 USA

ISBN: (纸本)9781509060238

Physical unclonable functions (PUFs) take advantage of the effect of process variation on hardware to obtain their unclonability. Traditional PUF design only focuses on the analog signals of circuits. An arbiter PUF, for example, generates responses by racing delay signals. Implementations of such PUFs usually employ large area and power consumption while providing very low throughput. To address this problem, we propose an energy efficient PUF design in such a way that it races analog signals and computes digital logic simultaneously. More importantly, the analog portion of the circuit (racing) shares a large amount of hardware resources with the digital portion of the circuit (computing) by introducing only small overhead in terms of area and power. Our test results on Spartan-6 field-programmable gate array (FPGA) platforms indicate that by combining the two outputs, our design enables much larger PUF output throughput, better randomness and less power consumption compared to traditional PUFs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Invited Paper: Ultra-low Energy Security Circuit Primitives for IoT Platforms 22

Invited Paper: Ultra-low Energy Security Circuit Primitives ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mathew, Sanu Satpathy, Sudhir Suresh, Vikram Krishnamurthy, Ram Intel Corp Circuits Res Lab Hillsboro OR 97124 USA

ISBN: (纸本)9781509060238

Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve > 0.99 min-entropy with 3pJ/bit energy-efficiency.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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CORAL: Coarse-grained Reconfigurable Architecture for ConvoLutional Neural Networks 22

CORAL: Coarse-grained Reconfigurable Architecture for ConvoL...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Yuan, Zhe Liu, Yongpan Yue, Jinshan Li, Jinyang Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781509060238

Convolutional Neural Network (CNN) has become one of the most successful technologies for visual classification and other applications. As CNN models continue to evolve and adopt different kernel sizes in various applications, it is necessary for the hardware architecture to support reconfigurability. Previous FPGAs and programmable ASICs are fine-grained reconfigurable but with energy efficiency compromise. Considering specific features of CNNs, this paper presents an energy efficient coarse-grained reconfigurable architecture, denoted as CORAL. An application-specific configuration neural block is proposed for convolution operations with reconfigurable data quantization to reduce both energy consumption and on-chip memory requirements. An optimal data loading strategy is presented for CORAL to achieve the best energy efficiency. Experimental results show that CORAL improves 80.0% energy efficiency while reduces 78.9% chip area and 81.0% reconfiguration time compared with the best up-to-date programmable ASIC solution.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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ASAP: Accelerated Short Read Alignment on programmable Hardware 17

ASAP: Accelerated Short Read Alignment on Programmable Hardw...

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acm/sigda international symposium on field-programmable gate arrays

作者： Banerjee, Subho S. el-Hadedy, Mohamed Lim, Jong B. Chen, Daniel Kalbarczyk, Zbigniew T. Chen, Deming Iyer, Ravishankar K. Univ Illinois Champaign IL USA

ISBN: (纸本)9781450343541

The proliferation of high-throughput sequencing machines allows for the rapid generation of billions of short nucleotide fragments in a short period. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This poster explores the use of hardware acceleration to significantly improve the runtime of short-read alignment (SRA), a crucial step in pre-processing sequenced genomes. It presents the design and implementation of ASAP, an accelerator for computing Levenshtein distance (LD) in the context of the SRA problem. LD computation is a prominent underlying mathematical kernel that is common to a large number of SRA tools (e.g., BLAST, BWA, SNAP) and is responsible for 50-70% of their runtime. These algorithms mentioned above calculate the exact value of LD between nucleotide strings but only use them to build a total ordering (an ordered list) of the most likely point of origin in the genome. ASAP computes an approximation of LD by encoding computation in propagation delay of circuit elements. This approximation is calculated in an accelerated fashion in hardware and preserves the original total ordering of LDs produced by the traditional algorithms. This computation is performed by constructing circuits that comprise the recursive definition of the LD computation and measuring propagation delay of a signal entering and leaving the circuit. Additionally, ASAP can explore large portions of the search space (substrings of the strings being compared) within one clock cycle, and ignore parts of the search space that does not contribute to an answer. Our design is implemented on an Altera Stratix V FPGA in an IBM POWER8 system using the CAPI interface for cache coherence across the CPU and FPGA. Our design is 200x faster (median measurement) than the equivalent C implementation of the kernel running on the host processor and 2.2x faster for an end-to-end alignment tool for 120-150bp short-read sequences.

关键词： FPGA Bioinformatics Genomics

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Battery Assignment and Scheduling for Drone Delivery Businesses 22

Battery Assignment and Scheduling for Drone Delivery Busines...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Park, Sangyoung Zhang, Licong Chakraborty, Samarjit Tech Univ Munich Chair Real Time Comp Syst Munich Germany

ISBN: (纸本)9781509060238

Recent advances in battery and drone technologies have opened up possibilities of commercial use of drones. Private companies are looking into the possibilities of using drones for commercial deliveries from the legal, technical, and economical perspective. Nevertheless, the battery management perspective of such businesses has not yet been thoroughly investigated. In this paper, we identify that battery management of such application has a major impact of the costs, and formulate an optimization problem to reduce the aging of batteries. We identify two subproblems, battery assignment, and battery scheduling to derive a solution that minimizes the aging of the batteries. We show that the formulation enables leveraging the trade-off relationships between the packet waiting time and battery purchasing cost. The experimental results show the proposed method reduce the electricity and battery purchasing cost by 25%, and average packet waiting time by more than 50%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology 22

Low Design Overhead Timing Error Correction Scheme for Elast...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ryu, Sungju Koo, Jongeun Kim, Jae-Joon Pohang Univ Sci & Technol Pohang South Korea

ISBN: (纸本)9781509060238

The elastic clock scheme is a robust design methodology to ensure timing closure under PVT variation using locally generated clocks and handshaking protocol. However, it still has a chance of timing errors due to delay mismatch between the data-path and delay replica. In this paper, we propose a low design overhead timing error correction scheme tailored to elastic clock. In the proposed scheme, a timing error can be corrected within a cycle using clock stretching. The proposed scheme shows 40.3X and 4.6X reduction in timing margin with 9.1% and 9.0% area overhead over the synchronous baseline and elastic clock design, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Hotspot Monitoring and Temperature Estimation with Miniature On-Chip Temperature Sensors 22

Hotspot Monitoring and Temperature Estimation with Miniature...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chundi, Pavan Kumar Zhou, Yini Kim, Martha Kursun, Eren Seok, Mingoo Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781509060238

This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Improved Clocking Methodology for Energy Efficient Low Area AES Architectures using Register Renaming 22

An Improved Clocking Methodology for Energy Efficient Low Ar...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Dhanuskodi, Siva Nishok Holcomb, Daniel Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781509060238

Sub-round implementations of AES have been explored as an area and energy efficient solution to encrypt data in resource constrained applications such as the Internet of Things. Symmetry in AES operations across bytes and words allows the datapath to be scaled down to 8 bits resulting in very compact designs. However, such designs incur an area penalty to store intermediate results or energy penalty to shift data through registers without performing useful computation. We propose a smart clocking scheme and rename registers to minimize data movement and clock loading, and also avoid storing a duplicate copy of the system state. In comparison to the most efficient 8-bit implementation from literature, we save 45% energy per encryption and reduce clock energy by 70% at a reasonable area cost.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O 22

Enabling Efficient Fine-Grained DRAM Activations with Interl...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Zhang, Chao Guo, Xiaochen Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA

ISBN: (纸本)9781509060238

DRAM contributes a significant part of the total system energy consumption, and row activation is one of the most energy inefficient components. Prior works on fine-grained DRAM activation rely on increasing the number of local wires to avoid degrading performance, which adds area overheads. This work proposes interleaved I/O to allow data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture allows half-, quarter-, or one-eighth-page activations without changing the wires. The system performance is competitive as compared with other finegrained activation designs. For the evaluated benchmarks, an average of up to 15.7% performance improvement is achieved among all of the configurations. Furthermore, the total DRAM energy can be reduced by an average of 11.2% for halfpage, 17.2% for quarterpage, and 22.3% for one-eighth-page.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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