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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs 22

Frequency and Time Domain Analysis of Power Delivery Network...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Das, Shidhartha Sinha, Saurabh Cline, Brian Yeric, Greg Lim, Sung Kyu Georgia Inst Teehnol Sch ECE Atlanta GA 30332 USA ARM Ltd Cambridge England ARM Inc Austin TX USA

ISBN: (纸本)9781509060238

As 2D scaling reaches its limit, monolithic 3D IC (M3D) is a leading contender to continue equivalent scaling. AIthough M3D shows power and performance benefits over 2D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power-supply integrity. In addition, we present frequency- and time-domain analysis of the M3D PDN. We show that the additional resistance in the M3D PDN, while being worse for resistive drops, improves resiliency against current noise showing 35.9% peak impedance reduction during worst-case resonant oscillations.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Full Chip Power Benefits with Negative Capacitance FETs 22

Full Chip Power Benefits with Negative Capacitance FETs

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Samal, Sandeep K. Khandelwal, Sourabh Khan, Asif I. Salahuddin, Sayeef Hu, Chenming Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Macquarie Univ Dept Engn Sydney NSW Australia Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)9781509060238

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercialgrade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4X (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Temporal Codes in On-Chip Interconnects 22

Temporal Codes in On-Chip Interconnects

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mishkin, Michael Kim, Nam Sung Lipasti, Mikko Univ Wisconsin Madison Madison WI USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781509060238

Dynamic power consumption associated with signal toggles over long distance wires accounts for a significant portion of onchip interconnect power. Improving dynamic energy efficiency in highly capacitive interconnects can be achieved by reducing the toggle rates associated with data communication. Temporal coding schemes facilitate bounded activity factors by encoding information as placement of signal toggles in time and can thereby improve the energy efficiency of data communication by encoding multiple bits per toggle. We introduce two temporal protocol variants designed for traversal of the crossbars in on-chip networks. These protocols reduce peak power without loss of bandwidth and achieve energy efficient onchip communication in high capacitance long distance interconnects. Extending these energy savings to a multi-hop mesh topology is achieved by router implementations equipped with bypassing mechanisms that elide per hop reencoding overheads. We demonstrate a four bit per transition temporal protocol with up to 75% communication energy reduction that can be achieved over a baseline serial bit stream protocol.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Efficient Query Processing in Crossbar Memory 22

Efficient Query Processing in Crossbar Memory

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Imani, Mohsen Gupta, Saransh Arredondo, Atl Rosing, Tajana Univ Calif San Diego CSE Dept La Jolla CA 92093 USA

ISBN: (纸本)9781509060238

Today's computing systems use huge amount of energy and time to process basic queries in database. A large part of it is spent in data movement between the memory and processing cores, owing to the limited cache capacity and memory bandwidth of traditional computers. In this paper, we propose a non-volatile memory-based query accelerator, called NVQuery, which performs several basic query functions in memory including aggregation, prediction, bit-wise operations, as well as exact and nearest distance search queries. NVQuery is implemented on a content addressable memory (CAM) and exploits the analog characteristic of non-volatile memory in order to enable in-memory processing. To implement nearest distance search in memory, we introduce a novel bitline driving scheme to give weights to the indices of the bits during the search operation. Our experimental evaluation shows that, NVQuery can provide 49.3x performance speedup and 32.9x energy savings as compared to running the same query on traditional processor. In addition, compared to the state-of-the-art query accelerators, NVQuery can achieve 26.2x energy-delay product improvement while providing the similar accuracy.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Exploring Sparsity of Firing Activities and Clock Gating for Energy-Efficient Recurrent Spiking Neural Processors 22

Exploring Sparsity of Firing Activities and Clock Gating for...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Liu, Yu Jin, Yingyezhe Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781509060238

As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its FPGA implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed FPGA-based neural processor system is up to 2 9 % more energy efficient than a baseline LSM processor with little extra hardware overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Energy-efficient and High-throughput Bitwise CNN on Sneak-path-free Digital ReRAM Crossbar 22

An Energy-efficient and High-throughput Bitwise CNN on Sneak...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ni, Leibin Liu, Zichuan Song, Wenhao Yang, J. Joshua Yu, Hao Wang, Kanwen Wang, Yuangang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Huawei Technol Co Ltd Data Ctr Technol Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781509060238

Convolutional neural network (CNN) based machine learning requires a highly parallel as weIl as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM cross bar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of I-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91. 4% accuracy on MNIST and CIFAR-IO benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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QuARK: Quality-configurable Approximate STT-MRAM Cache by Fine-grained Tuning of Reliability-Energy Knobs 22

QuARK: Quality-configurable Approximate STT-MRAM Cache by Fi...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Monazzah, Amir Mahdi Hosseini Shoushtari, Majid Miremadi, Seyed Ghassem Rahmani, Amir M. Dutt, Nikil Sharif Univ Technol Dept Comp Engn Tehran Iran TU Wien Inst Comp Technol Vienna Austria Univ Calif Irvine Dept Comp Sci Irvine CA USA

ISBN: (纸本)9781509060238

Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/ write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This paper proposes QuARK, a hardware/ software approach for trading reliability of STT-MRAM caches for energy savings in the on-chip memory hierarchy of multi-and many-core systems running approximate applications. In contrast to SRAM-based cache-way-level actuators, QuARK utilizes fine-grained cache-line-level actuation knobs with different levels of reliability for individual read and write accesses which are unique to STT-MRAM and suitable for systems running multiple applications with mixed accuracy sensitivity, thus avoiding interapplication actuation interference. Our experimental results with a set of recognition, mining and synthesis (RMS) benchmarks demonstrate up to 40% energy savings over a fully-protected STT-MRAM cache, with negligible loss in the quality of the generated outputs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Design High Bandwidth-Density, Low Latency and Energy Efficient On-Chip Interconnect 22

Design High Bandwidth-Density, Low Latency and Energy Effici...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Wang, Yong Wu, Hui Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781509060238

For future high-performance computing chips, onchip interconnect requires large bandwidth-density, low latency, and high energy-efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on-chip interconnect. First, we conduct an optimization of on-chip transmission lines to minimize the size, channel loss and inter-symbol-interference (ISI), hence to maximize the bandwidth-density. Based on the result, differential coplanar waveguide (CPW) with 55-mu m pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time-domain pulse responses. Various equalizers are studied, which are used to increase the ISI-limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non-returnto- zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28-nm CMOS technology. An 84-Gb/s PAM-8 transceiver achieves 1.5Gb/ s/mu m bandwidth-density over a 4-cm channel. The unrepeated bandwidth-density is 6.1 Gb/s/mu m-cm, which is almost 10 times larger compared to prior work.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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AXSERBUS: A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensing 22

AXSERBUS: A Quality-Configurable Approximate Serial Bus for ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Kim, Younghyun Behroozi, Setareh Raghunathan, Vijay Raghunathan, Anand Univ Wisconsin Dept Elect & Comp Engn Maison WI 53706 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Mobile, wearable, and implantable devices integrate an increasing number and variety of sensors such as microphones, image sensors, and accelerometers. These devices spend substantial amounts of time reading the sensors within them, thereby incurring significant energy dissipation over off-chip serial interconnects. This paper proposes AXSERBUS, a quality-configurable approximate serial bus that exploits the locality of sensory data and the error resiliency of sensing applications to reduce energy dissipation. AXSERBUS significantly reduces signal transitions by encoding the differentials of sensory data in three encoding modes, depending on the magnitude of the differentials: very small differentials are zeroed out, incurring no energy dissipation;intermediate differentials are encoded using special low-transition count patterns;and for high differentials, the absolute value (not the differential) of the data is transmitted. Compared to previous schemes, the proposed multi-level encoding results in more data being encoded as low-energy patterns. In addition, in the intermediate differential encoding mode, the differentials are encoded in an approximate manner, and the approximation bounds are proportional to the magnitude of the differentials. Since small differentials are more frequent than large differentials in sensory data, the proposed encoding scheme also minimizes quality degradation. We demonstrate that AXSERBUS achieves improved energy vs. quality tradeoffs compared to previous schemes. In the context of an optical character recognition (OCR) application, AXSERBUS achieves 79.4% reduction in dynamic power dissipation, while maintaining accuracy above 95%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Approximate Memory Compression for Energy-efficiency 22

Approximate Memory Compression for Energy-efficiency

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ranjan, Ashish Raha, Arnab Raghunathan, Vijay Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Memory subsystems are a major energy bottleneck in computing platforms due to frequent transfers between processors and off-chip memory. We propose approximate memory compression, a technique that leverages the intrinsic resilience of emerging workloads such as machine learning and data analytics to reduce off-chip memory traffic and energy. To realize approximate memory compression, we enhance the memory controller to be aware of memory regions that contain approximation-resilient data, and to transparently compress/decompress the data written to/read from these regions. To provide control over approximations, the quality-aware memory controller conforms to a specified error constraint for each approximate memory region. We design a software interface that programmers can use to identify data structures that are resilient to approximations. We also propose a runtime quality control framework that automatically determines the error constraints for the identified data structures such that a given target application-level quality is maintained. We evaluate our proposal by implementing a hardware prototype using the Intel UniPHY-DDR3 memory controller and NIOS-II processor, a Hynix DDR3 DRAM module, and a Stratix-IV FPGA development board. Across a suite of 8 machine learning benchmarks, approximate memory compression obtains a 1.28 x benefit in DRAM energy and a simultaneous 11.5% improvement in execution time for a small (< 1.5%) loss in output quality.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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