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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是181-190 订阅

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An Energy-efficient and High-throughput Bitwise CNN on Sneak-path-free Digital ReRAM Crossbar 22

An Energy-efficient and High-throughput Bitwise CNN on Sneak...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ni, Leibin Liu, Zichuan Song, Wenhao Yang, J. Joshua Yu, Hao Wang, Kanwen Wang, Yuangang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Huawei Technol Co Ltd Data Ctr Technol Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781509060238

Convolutional neural network (CNN) based machine learning requires a highly parallel as weIl as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM cross bar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of I-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91. 4% accuracy on MNIST and CIFAR-IO benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition 22

Monolithic 3D IC Designs for Low-Power Deep Neural Networks ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Kadetotad, Deepak Cao, Yu Seo, Jae-sun Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Arizona State Univ Sch ECEE Tempe AZ USA

ISBN: (纸本)9781509060238

In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic 22

A Carbon Nanotube Transistor based RISC-V Processor using Pa...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Amarnath, Aporva Feng, Siying Pal, Subhankar Ajayi, Tutu Rovinski, Austin Dreslinski, Ronald G. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509060238

With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over siliconbased counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energyefficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9. EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5x as well as reduce area by 17% over 16 nm silicon CMOS.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads 22

Online Tuning of Dynamic Power Management for Efficient Exec...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Bantock, James R. B. Tenentes, Vasileios Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Dept Elect & Comp Sci Southampton Hants England

ISBN: (纸本)9781509060238

Modern mobile devices contain powerful MultiProcessor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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SceneMan: Bridging Mobile Apps with System Energy Manager via Scenario Notification 22

SceneMan: Bridging Mobile Apps with System Energy Manager vi...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Li, Li Wang, Jun Wang, Xiaorui Ye, Handong Hu, Ziang Ohio State Univ Columbus OH 43210 USA Huawei US R&D Santa Clara CA USA

ISBN: (纸本)9781509060238

Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Power Optimizations in MTJ-based Neural Networks through Stochastic Computing 22

Power Optimizations in MTJ-based Neural Networks through Sto...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Mondal, Ankit Srivastava, Ankur Univ Maryland Dept Elect & Comp Engn College Pk MD 20783 USA

ISBN: (纸本)9781509060238

Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. Spintronic devices, such as Magnetic Tunnel Junctions (MTJs), are capable of replacing CMOS in memory and logic circuits. In this work, we propose an energy-efficient use of MTJs, which exhibit probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, error resilient target applications of NNs allow us to introduce Approximate Computing, a framework wherein accuracy of computations is traded-off for substantial reductions in power consumption. We propose approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of our MTJ-SNG, to achieve energy-efficiency. We design an algorithm that can perform such approximations within a given error tolerance in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. To give a perspective of the effectiveness of our approach, a 43% reduction in power consumption was obtained with less than 1% accuracy loss on a standard classification problem, with 26% being brought about by the proposed algorithm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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OLAF′16: Second international Workshop on Overlay Architectures for FPGAs 16

OLAF′16: Second International Workshop on Overlay Architect...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450338561

The Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: The 24th acm/sigda international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.

关键词： FPGA Overlay architecture

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Reconfigurable Thermoelectric Generators for Vehicle Radiators Energy Harvesting 22

Reconfigurable Thermoelectric Generators for Vehicle Radiato...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Baek, Donkyu Ding, Caiwen Lin, Sheng Shin, Donghwa Kim, Jaemin Lin, Xue Wang, Yanzhi Chang, Naehyuck Korea Adv Inst Sci & Technol Daejeon South Korea Syracuse Univ Syracuse NY USA Yeungnam Univ Gyongsan South Korea Seoul Natl Univ Seoul South Korea Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781509060238

Conventional internal combustion engine vehicles (ICEV) generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The heat energy maintains the engine temperature for efficient combustion as a good aspect, but the amount of heat generation is excessive and eventually breaks the engine components unless advanced cooling system technologies are supported such as high- capacity radiators, elaborated water jackets, high- flow rate coolant pumps, etc. The excessive heat dissipation plays a key role on a poor fuel economy, but reclamation of the heat energy has not been a main focus of vehicle design. This work is first to propose a cross-layer, system-level solution to enhance thermoelectric generator (TEG) array efficiency introducing online reconfiguration of TEG modules. The proposed method is useful to any sort of TEG array to reclaim wasted heat energy because cooling and exhaust systems generally have different inlet and outlet temperatures. In this paper, we deploy the proposed method to vehicle radiator heat energy harvesting, which does not affect the vehicle performance while exhaust heat energy harvesting may disturb the combustion and emission control integrity. We introduce a novel TEG reconfiguration and maximize the TEG array output in spite of dynamic change of the coolant flow rate and temperature, which results in a huge variation in the coolant temperature distribution of inside the radiator. The proposed method enables all the TEG modules to run at or close to their maximum power points (MPP) under dynamically changing vehicle operating conditions. Experimental results show up to a 34% enhancement compared with a fixed array structure, which is a common practice.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Towards PVT-Tolerant Glitch-Free Operation in FPGAs 16

Towards PVT-Tolerant Glitch-Free Operation in FPGAs

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Huda, Safeen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450338561

Glitches are unnecessary transitions on logic signals that needlessly consume dynamic power. Glitches arise from imbalances in the combinational path delays to a signal, which may cause the signal to toggle multiple times in a given clock cycle before settling to its final value. In this paper, we propose a low-cost circuit structure that is able to eliminate a majority of glitches. The structure, which is incorporated into the output buffers of FPGA logic elements, suppresses pulses on buffer outputs whose duration is shorter than a configurable time window (set at the time of FPGA configuration). Glitches are thereby eliminated "at the source" ensuring they do not propagate into the high-capacitance FPGA interconnect, saving power. An experimental study, using Altera commercial tools for power analysis, demonstrates that the proposed technique reduces 70% of glitches, at a cost of 1% reduction in speed performance.

关键词： field programmable gate arrays (FPGA)

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. This allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (FPGA)

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