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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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High-level design tools for floating point FPGAs 15

High-level design tools for floating point FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Singh, Deshanand P. Pasca, Bogdan Czajkowski, Tomasz S. Altera Corporation 150 Bloor Street West TorontoON Canada Altera Corporation Westwood High Wycombe BuckinghamshireHP12 4PU United Kingdom

ISBN: (纸本)9781450333153

This tutorial describes tools for efficiently implementing floating point applications on FPGAs. We present both the SDK for OpenCL and DSP Builder Advanced Blockset and show that they can be effectively used to implement many floating point applications. The methods for optimizing application performance are also described. In this tutorial we focus on a few applications, including Fast Fourier transform, matrix multiplication, finite impulse response filter and a Cholesky decomposition. In all cases we show what the tools are capable of achieving, and more importantly how a user can take advantage of the various floating-point centric features that are made available. We also discuss how these tools can automatically use FPGA architectural features such as hardened floating-point DSP available on Altera Arria 10 family. © Copyright 2015 acm.

关键词： field programmable gate arrays (FPGA)

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Technology mapping into general programmable cells 15

Technology mapping into general programmable cells

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Mishchenko, Alan Brayton, Robert Feng, Wenyi Greene, Jonathan Department of EECS University of California Berkeley United States Microsemi Corporation SOC Products Group United States

ISBN: (纸本)9781450333153

field-programmable gate arrays (FPGA) implement logic functions using programmable cells, such as K-input lookuptables (K-LUTs). A K-LUT can implement any Boolean function with K inputs and one output. Methods for mapping into K-LUTs are extensively researched and widely used. Recently, cells other than K-LUTs have been explored, for example, those composed of several LUTs and those combining LUTs with several gates. Known methods for mapping into these cells are specialized and complicated, requiring a substantial effort to evaluate custom cell architectures. This paper presents a general approach to efficiently map into single-output K-input cells containing LUTs, MUXes, and other elementary gates. Cells with to 16 inputs can be handled. The mapper is fully automated and takes a logic network and a symbolic description of a programmable cell, and produces an optimized network composed of instances of the given cell. Past work on delay/area optimization during mapping is applicable and leads to good quality of results.

关键词： Boolean functions

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Floating-point DSP block architecture for FPGAs 15

Floating-point DSP block architecture for FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre United Kingdom

ISBN: (纸本)9781450333153

This work describes the architecture of a new FPGA DSP block supporting both fixed and floating point arithmetic. Each DSP block can be configured to provide one single precision IEEE-754 floating multiplier and one IEEE-754 floating point adder, or when configured in fixed point mode, the block is completely backwards compatible with current FPGA DSP blocks. The DSP block operating frequency is similar in both modes, in the region of 500MHz, offering up to 2 GMACs fixed point and 1 GFLOPs performance per block. In floating point mode, support for multi-block vector modes are provided, where multiple blocks can be seamlessly assembled into any size real or complex dot products. By efficient reuse of the fixed point arithmetic modules, as well as the fixed point routing, the floating point features have only minimal power and area impact. We show how these blocks are implemented in a modern Arria 10 FPGA family, offering over 1 TFLOPs using only embedded structures, and how scaling to multiple TFLOPs densities is possible for planned devices. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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On data forwarding in deeply pipelined soft processors 15

On data forwarding in deeply pipelined soft processors

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Cheah, Hui Yan Fahmy, Suhaib A. Kapre, Nachiket School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781450333153

We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives, supported by selective data forwarding, to deliver up to 25% performance improvements across a range of benchmarks. Pipelined, inorder, scalar processors can be small and lightweight but suffer from a large number of idle cycles due to dependency chains in the instruction sequence. Data forwarding allows us to more deeply pipeline the processor stages while avoiding an associated increase in the NOP cycles between dependent instructions. Full forwarding can be prohibitively complex for a lean soft processor, so we explore two approaches: an external forwarding path around the DSP block execution unit in FPGA logic and using the intrinsic loopback path within the DSP block primitive. We show that internal loopback improves performance by 5% compared to external forwarding, and up to 25% over no data forwarding. The result is a processor that runs at a frequency close to the fabric limit of 500MHz, but without the significant dependency overheads typical of such processors. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Superoptimized memory subsystems for streaming applications 15

Superoptimized memory subsystems for streaming applications

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wingbermuehle, Joseph G. Cytron, Ron K. Chamberlain, Roger D. Dept. of Computer Science and Engineering Washington University in St. Louis United States

ISBN: (纸本)9781450333153

Because main memory is many times slower than modern processor cores, deep, multi-level cache hierarchies are ubiquitous in computers today. Similarly, applications deployed on ASICs and FPGAs are often hindered by slow external memories. Therefore, to achieve good performance, hardware designers must optimize main memory usage. Unfortunately, this process is often labor intensive and fails to explore the full range of potential memory designs. To address this issue for applications expressed in a streaming manner, we show that it is possible to generate automatically a superoptimized memory subsystem that can be deployed on an FPGA such that it performs better than a general-purpose memory subsystem. Rather than explore only simple memory subsystems, our superoptimizer is capable of exploring extremely complex designs consisting of multi-level caches and other components. Finally, we show that it is possible to deploy applications with superoptimized memory subsystems with minimal additional effort while achieving significant performance improvements over a naive memory subsystem.

关键词： field programmable gate arrays (FPGA)

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Enhancements in UltraScale CLB architecture 15

Enhancements in UltraScale CLB architecture

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chandrakar, Shant Gaitonde, Dinesh Bauer, Trevor Xilinx Inc. Hyderabad India Xilinx Inc. San JoseCA United States Xilinx Inc. LongmontCO United States

ISBN: (纸本)9781450333153

Each generation of FPGA architecture benefits from optimizations around its technology node and target usage. In this paper, we discuss some of the changes made to the CLB for Xilinx's 20nm UltraScale product family. We motivate those changes and demonstrate better results than previous CLB architectures on a variety of metrics. We show that, in demanding scenarios, logic placed in an UltraScale device requires 16% less wirelength than 7-series. Designs mapped to UltraScale devices also require fewer logic tiles. In this paper, we demonstrate the utilization benefits of the Ultra-Scale CLB attributed to certain CLB enhancements. The enhancements described herein result in an average packing improvement of 3% for the example design suite. We also show that the UltraScale architecture handles aggressive, tighter packing more gracefully than previous generations of FPGA. These significant reductions in wirelength and CLB counts translate directly into power, performance and ease-of-use benefits.

关键词： field programmable gate arrays (FPGA)

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Fine-grained interconnect synthesis 15

Fine-grained interconnect synthesis

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Rodionov, Alex Biancolin, David Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Canada

ISBN: (纸本)9781450333153

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis tool that automates this process and focuses on the interconnect needs in the fine-grained (sub-IP-block) design space. Here there are several issues that prior research and tools do not address well: the need to have fixed, deterministic latency between communicating units (to enable high-performance local communication without the area overheads of latency-insensitivity), and the ability to avoid generating un-necessary arbitration hardware when the application design can avoid it. Using a design example, our tool generates interconnect that requires 72% fewer lines of specification code than a hand-written Verilog implementation, which is a 33% overall reduction for the entire application. The resulting system, while requiring 4% more total functional and interconnect area, achieves the same performance. We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 17%/57% logic/memory area savings.

关键词： field programmable gate arrays (FPGA)

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InTime: A machine learning approach for efficient selection of FPGA CAD tool parameters 15

InTime: A machine learning approach for efficient selection ...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Kapre, Nachiket Ng, Harnhua Teo, Kirvy Naude, Jaco Nanyang Technological University Singapore Singapore Plunify Inc. Singapore Singapore

ISBN: (纸本)9781450333153

FPGA CAD tool parameters controlling synthesis optimizations, place and route effort, mapping criteria along with user-supplied physical constraints can affect timing results of the circuit by as much as 70% without any change in original source code. A correct selection of these parameters across a diverse set of benchmarks with varying characteristics and design goals is challenging. The sheer number of parameters and option values that can be selected is large (thousands of combinations for modern CAD tools) with often conflicting interactions. In this paper, we present InTime, a machinelearning approach supported by a cloud-based (or clusterbased) compilation infrastructure for automating the selection of these parameters effectively to minimize timing costs. InTime builds a database of results from a series of preliminary runs based on canned configurations of CAD options. It then learns from these runs to predict the next series of CAD tool options to improve timing results. Towards the end, we rely on a limited degree of statistical sampling of certain options like placer and synthesis seeds to further tighten results. Using our approach, we show 70% reduction in final timing results across industrial benchmark problems for the Altera CAD flow. This is 30% better than vendor-supplied design space exploration tools that attempts a similar optimization using canned heuristics. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Mapping-aware constrained scheduling for LUT-based FPGAs 15

Mapping-aware constrained scheduling for LUT-based FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Tan, Mingxing Dai, Steve Gupta, Udit Zhang, Zhiru School of Electrical and Computer Engineering Cornell University IthacaNY United States

ISBN: (纸本)9781450333153

Scheduling plays a central role in high-level synthesis, as it inserts clock boundaries into the untimed behavioral model and greatly impacts the performance, power, and area of the synthesized circuits. While current scheduling techniques can make use of pre-characterized delay values of individual operations, it is difficult to obtain accurate timing estimation on a cluster of operations without considering technology mapping. This limitation is particularly pronounced for FPGAs where a large logic network can be mapped to only a few levels of look-up tables (LUT). In this paper, we propose MAPS, a mapping-aware constrained scheduling algorithm for LUT-based FPGAs. Instead of simply summing up the estimated delay values of individual operations, MAPS jointly performs technology mapping and scheduling, creating the opportunity for more aggressive operation chaining to minimize latency and reduce area. We show that MAPS can produce a latency-optimal solution, while supporting a variety of design timing requirements expressed in a system of difference constraints. We also present an efficient incremental scheduling technique for MAPS to effectively handle resource constraints. Experimental results with real-life benchmarks demonstrate that our proposed algorithm achieves very promising improvements in performance and resource usage when compared to a state-of-the-art commercial high-level synthesis tool targeting Xilinx FPGAs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Application of specific delay window routing for timing optimization in FPGA designs 15

Application of specific delay window routing for timing opti...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wegley, Evan Zhang, Qinhai Lattice Semiconductor Corporation 2115 O'Nel Drive San JoseCA95131 United States

ISBN: (纸本)9781450333153

In addition to optimizing for timing performance and routability, commercial FPGA routing engines must also support various timing constraints enabling the designer to fine tune aspects of their design. The many intricacies of commercial FPGA architectures add difficulty to the problem of supporting such constraints. In this paper, we show how the method of specific delay window routing can be applied to optimize for these various timing constraints constituting both long-and short-path requirements. Additionally, we enhance existing methods of routing according to specified delay by using dual wave expansion instead of single wave expansion with target delay estimation in order to improve accuracy and support sparser, more varied interconnect structures. Our results show that specific delay window routing is well-suited for optimization targeting a variety of timing constraints, and that using dual wave expansion to eliminate the estimation part of the router's delay cost function enables the router to support tighter timing constraints. For a suite of designs with known hold timing violations, we found that the dual wave approach can correct all such violations, whereas the single wave approach failed to correct the hold timing violations for several designs. Furthermore, for a suite of designs with maximum skew constraints of 250 ps on certain nets and buses, the dual wave approach met the constraints for all designs, whereas the single wave approach failed to meet the constraints for a majority of the designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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