检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

578 篇 会议
31 篇 期刊文献

馆藏范围

609 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

522 篇 工学
- 470 篇 计算机科学与技术...
- 289 篇 软件工程
- 228 篇 电子科学与技术（可...
- 157 篇 电气工程
- 86 篇 信息与通信工程
- 36 篇 控制科学与工程
- 35 篇 动力工程及工程热...
- 23 篇 机械工程
- 14 篇 生物工程
- 12 篇 仪器科学与技术
- 10 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 5 篇 材料科学与工程（可...
- 3 篇 农业工程
201 篇 理学
- 166 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 15 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
57 篇 管理学
- 48 篇 管理科学与工程(可...
- 30 篇 工商管理
- 10 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 教育学
- 3 篇 教育学
3 篇 农学
1 篇 医学

主题

261 篇 field programmab...
174 篇 field programmab...
39 篇 clocks
35 篇 signal processin...
34 篇 estimation
34 篇 filtration
33 篇 modulation
33 篇 ofdm
31 篇 fpga
8 篇 field-programmab...
7 篇 fpgas
7 篇 computer archite...
7 篇 systolic arrays
7 篇 optimization
7 篇 high-level synth...
7 篇 field-programmab...
7 篇 reconfigurable c...
6 篇 hardware
6 篇 field programmab...
5 篇 routing

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 xilinx
4 篇 univ british col...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 pasca bogdan
7 篇 constantinides g...
7 篇 chow paul
6 篇 wilton steven j....
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

601 篇 英文
8 篇 其他

检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是211-220 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Delay-bounded routing for shadow registers 15

Delay-bounded routing for shadow registers

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Hung, Eddie Levine, Joshua M. Stott, Edward Constantinides, George A. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College London United Kingdom Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9781450333153

The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Energy-efficient discrete signal processing with field programmable analog arrays (FPAAs) 15

Energy-efficient discrete signal processing with field progr...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Bai, Yu Lin, Mingjie Department of Electrical Engineering and Computer Science University of Central Florida OrlandoFL32765 United States

ISBN: (纸本)9781450333153

Large-scale field programmable analog array (FPAA) devices have made analog and analog-digital signal processing techniques accessible to a much wider community. However, largely due to its severe resource constraints, high noise sensitivity, and enormous design space, reconfigurable analog computing remains a niche in the DSP application space. In this paper, we develop a probabilistic-based methodology for designing and implementing the analog computing engines that specifically target at energy-efficient signal processing systems. We will first demonstrate how to decompose a given DSP application into various functional modules within the framework of probabilistic-based processing. Furthermore, we will show how these individual functional modules can be easily mapped to the limited selection of analog blocks found in an commercially available FPAA device: the PSoC chip platform from Cypress. To keep our study concrete, our implementation example focuses on the 1-D convolution module, a fundamental algorithmic building block in many applications of computer vision and artificial intelligence. In the end, we construct a complete image processing system based on the PSoC chip platform, and use the application of image key point extraction to demonstrate that our proposed approach to reconfigurable analog computing has considerable advantages in hardware usage, energy efficiency, and computing robustness over the traditional DSP approaches. © Copyright acm.

关键词： Digital signal processing

来源：评论

学校读者我要写书评

暂无评论

Energy and memory efficient mapping of bitonic sorting on FPGA 15

Energy and memory efficient mapping of bitonic sorting on FP...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chen, Ren Siriyal, Sruja Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles90089 United States

ISBN: (纸本)9781450333153

Parallel sorting networks are widely employed in hardware implementations for sorting due to their high data paral- lelism and low control overhead. In this paper, we propose an energy and memory efficient mapping methodology for implementing bitonic sorting network on FPGA. Using this methodology, the proposed sorting architecture can be built for a given data parallelism while supporting continuous data streams. We propose a streaming permutation network (SPN) by "folding" the classic Clos network. We prove that the SPN is programmable to realize all the interconnection patterns in the bitonic sorting network. A low cost design for sorting with minimal resource usage is obtained by reusing one SPN. We also demonstrate a high throughput design by trading off area for performance. With a data parallelism of p (2≤ p≤ N= log2 N), the high throughput design sorts an N-key sequence with latency O(N=p), throughput (# of keys sorted per cycle) O(p) and uses O(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) of O(p=N). Another noteworthy feature of the high throughput design is that only single-port memory rather than dual-port memory is required for processing continu- ous data streams. This results in 50% reduction in memory consumption. Post place-and-route results show that our architecture demonstrates 1.3x∼1.6x improvment in energy efficiency and 1.5x∼5.3x better memory efficiency compared with the state-of-the-art designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only) 16

Re-targeting Optimization Sequences from Scalar Processors t...

引用

proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Ronak Kogta Suresh Purini Ajit Mathew International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450338561

A high-level synthesis compiler translates a source program written in a high level programming language such as C or SystemC into an equivalent circuit. The performance of the generated circuit in terms of metrics such as area, frequency and clock cycles depends on the compiler optimizations enabled and their order of application. Finding an optimal sequence for a given program is a hard combinatorial optimization problem. In this paper, we propose a practical and search time efficient technique for finding a near-optimal sequence for a given program. The main idea is to strike a balance between the search for a universally good sequence (like that of O3) which works for all programs vis-a-vis finding a good sequence on a per-program basis. Towards that, we construct a rich downsampled sequence set, which caters to different program classes, from the unbounded optimization sequence space by applying heuristic search algorithms on a set of Microkernel benchmark programs. The optimization metric that we use while constructing the downsampled sequence set is the execution time on a scalar processor. Given a new program, we try all the sequences from the downsampled sequence setand pick the best. Applying this technique in the LegUp high-level synthesis compiler, we are able to obtain 23% and 40% improvement on CHStone and Machsuite benchmark programs respectively. We also propose techniques to further reduce the size of the downsampled sequence set to improve the sequence search time.

关键词： high level synthesis optimization compilers

来源：评论

学校读者我要写书评

暂无评论

Optimizing FPGA-based accelerator design for deep convolutional neural networks 15

Optimizing FPGA-based accelerator design for deep convolutio...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Zhang, Chen Li, Peng Sun, Guangyu Guan, Yijin Xiao, Bingjun Cong, Jason Center for Energy-Efficient Computing and Applications Peking University China Computer Science Department University of California Los Angeles United States PKU UCLA Joint Research Institute in Science and Engineering United States

ISBN: (纸本)9781450333153

Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapid growth of modern applications based on deep learning algorithms has further improved research and implementations. Especially, various accelerators for deep CNN have been proposed based on FPGA platform because it has advantages of high performance, reconfigurability, and fast development round, etc. Although current FPGA accelerators have demonstrated better performance over generic processors, the accelerator design space has not been well exploited. One critical problem is that the computation throughput may not well match the memory bandwidth provided an FPGA platform. Consequently, existing approaches cannot achieve best performance due to underutilization of either logic resource or memory bandwidth. At the same time, the increasing complexity and scalability of deep learning applications aggravate this problem. In order to overcome this problem, we propose an analytical design scheme using the rooine model. For any solution of a CNN design, we quantitatively analyze its computing throughput and required memory bandwidth using various optimization techniques, such as loop tiling and transformation. Then, with the help of rooine model, we can identify the solution with best performance and lowest FPGA resource requirement. As a case study, we implement a CNN accelerator on a VC707 FPGA board and compare it to previous approaches. Our implementation achieves a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

The Digital Bidirectional Function as a Hardware Security Primitive: Architecture and Applications 20

The Digital Bidirectional Function as a Hardware Security Pr...

引用

IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781467380096

Security and low power have emerged to become two essential requirements to modern design. In this paper, we have proposed a new hardware security primitive: digital bidirectional function (DBF) designed on FPGA to meet both criteria. The DBF has two forms of functions and implements two mappings of opposite directions. The DBF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. In terms of applications, we demonstrate how DBF is applied in the protocol of secure message transfer and compare its power/bandwidth consumption with other cryptographic approaches. Our results indicate that the energy consumption of DBF outperforms the traditional ciphers by averagely two to three orders of magnitude.

关键词： DESIGN BASIS FIRES hardware security modern design energy consumption message passing field programmable gate arrays Primitive Bidirectional

来源：评论

学校读者我要写书评

暂无评论

FPGA'12 - proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

引用

2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy FPGA-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on FPGA;incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on FPGAs;saturating the transceiver bandwidth: switch fabric design on FPGAs;limit study of energy & delay benefits of component-specific routing;impact of FPGA architecture on resource sharing in high-level synthesis;and securing netlist-level FPGA design through exploiting process variation and degradation.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

来源：评论

学校读者我要写书评

暂无评论

An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

来源：评论

学校读者我要写书评

暂无评论

Logic gates in the routing network of FPGAs (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of FPGA architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共61页 << < 18 19 20 21 22 23 24 25 26 27 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：