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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是231-240 订阅

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OmpSs@zynq all-programmable soc ecosystem

OmpSs@zynq all-programmable soc ecosystem

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Filgueras, Antonio Gil, Eduard Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Langer, Jan Noguera, Juanjo Vissers, Kees Barcelona Supercomputing Center Spain Universitat Politecnica de Catalunya Spain Xilinx Research Lab United States

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely inuenced the recently appeared OpenMP 4.0 specication. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benets DLP, ILP and TLP parallelisms in order to eciently exploit the new tech-nology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous ex-ecution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： System-on-chip

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FPGA place & route challenges 14

FPGA place & route challenges

引用

2014 acm international symposium on Physical Design, ISPD 2014

作者： Aggarwal, Rajat Xilinx Inc 2100 Logic Dr San Jose CA 95124 United States

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

ISBN: (纸本)9781450325929

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

关键词： field programmable gate arrays (FPGA)

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Rent's rule based FPGA packing for routability optimization 14

Rent's rule based FPGA packing for routability optimization

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Feng, Wenyi Greene, Jonathan Vorwerk, Kristofer Pevzner, Val Kundu, Arun Microsemi Corporation 3870 N 1st Street San Jose CA 95134 United States

ISBN: (纸本)9781450326711

Packing is a critical step in the CAD flow for cluster-based FPGA architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for FPGA packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

关键词： field programmable gate arrays (FPGA)

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Wordwidth, instructions, looping, and virtualization the role of sharing in absolute energy minimization 14

Wordwidth, instructions, looping, and virtualization the rol...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450326711

When are FPGAs more energy ecient than processors? This question is complicated by technology factors and the wide range of application characteristics that can be ex-ploited to minimize energy. Using a wire-dominated en-ergy model to estimate the absolute energy required for pro-grammable computations, we determine when spatially or-ganized programmable computations (FPGAs) require less energy than temporally organized programmable computa-tions (processors). The point of crossover will depend on the metal layers available, the locality, the SIMD wordwidth regularity, and the compactness of the instructions. When the Rent Exponent, p, is less than 0.7, the spatial design is always more energy ecient. When p = 0:8, the technology oers 8-metal layers for routing, and data can be organized into 16b words and processed in tight loops of no more than 128 instructions, the temporal design uses less energy when the number of LUTs is greater than 64K. We further show that heterogeneous multicontext architectures can use even less energy than the p = 0:8, 16b word temporal case.

关键词： field programmable gate arrays (FPGA)

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Hardware acceleration of database operations 14

Hardware acceleration of database operations

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Casper, Jared Olukotun, Kunle Pervasive Parallelism Laboratory Stanford University United States

ISBN: (纸本)9781450326711

As the amount of memory in database systems grows, en-tire database tables, or even databases, are able to t in the system's memory, making in-memory database operations more prevalent. This shift from disk-based to in-memory database systems has contributed to a move from row-wise to columnar data storage. Furthermore, common database workloads have grown beyond online transaction process-ing (OLTP) to include online analytical processing and data mining. These workloads analyze huge datasets that are of-ten irregular and not indexed, making traditional database operations like joins much more expensive. In this paper we explore using dedicated hardware to ac-celerate in-memory database operations. We present hard-ware to accelerate the selection process of compacting a sin-gle column into a linear column of selected data, joining two sorted columns via merging, and sorting a column. Finally, we put these primitives together to accelerate an entire join operation. We implement a prototype of this system using FPGAs and show substantial improvements in both absolute throughput and utilization of memory bandwidth. Using the prototype as a guide, we explore how the hardware resources required by our design change with the desired throughput.

关键词： field programmable gate arrays (FPGA)

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Square-rich fixed point polynomial evaluation on FPGAs 14

Square-rich fixed point polynomial evaluation on FPGAs

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Xu, Simin Fahmy, Suhaib A. McLoughlin, Ian V. Xilinx Asia Pacific Singapore School of Computer Engineering Nanyang Technological University Singapore School of Information Science and Technology University of Science and Technology of China China

ISBN: (纸本)9781450326711

Polynomial evaluation is important across a wide range of application domains, so signicant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial com-putation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an effcient polynomial evaluation algorithm, which reforms the evaluation process to include an increased num-ber of squaring steps. By using a squarer design that is more effcient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.

关键词： field programmable gate arrays (FPGA)

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A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs 14

A scalable sparse matrix-vector multiplication kernel for en...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Dorrance, Richard Ren, Fengbo Marković, Dejan EE Department UCLA Los Angeles CA 90095 United States

ISBN: (纸本)9781450326711

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

关键词： field programmable gate arrays (FPGA)

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A FPGA prototype design emphasis on low power technique 14

A FPGA prototype design emphasis on low power technique

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Hanyang, Xu Jian, Wang Jinmei, Lai Fudan University No.825 Zhangheng Rd shanghai China

ISBN: (纸本)9781450326711

In this paper, we propose a fully-functional Nanometer FPGA prototype chip. Compared to traditional single supply voltage, single threshold voltage design, we explore low power nanometer FPGA design challenges with Multi-Vt, Static Voltage Scaling and sleep mode technique. Compared to Dynamic Voltage Scaling (DVS), we make a table of Voltage-Delay parameter pairs under different voltage conditions so that timing information can be calculated by a Static Timing Analysis (STA) tool. Thus a lowest supply power is chosen among all results which meet the timing requirements. This approach would simplify the hardware design since we don't need a complex workload detection circuit compared to DVS system. By separating supply voltages, we can directly shutdown power supply of the unused circuits. Compared to inserting sleep transistor in pull-up or pull-down networks, we can eliminate the speed penalty cased by the additional sleep transistor. We implement a tile-based heterogeneous architecture with island style routing and embedded specific blocks such as DSP and memory. The array size is 6431 (RowCol) including 6424 CLBs. The final design is fabricated using a 1P10M 65-nm bulk CMOS process. Test results show a 53% reduction in static power compared to a commercial FPGA device which is also fabricated in 65nm process and has a similar array size.

关键词： field programmable gate arrays (FPGA)

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MPack: Global memory optimization for stream applications in high-level synthesis 14

MPack: Global memory optimization for stream applications in...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Vasiljevic, Jasmina Chow, Paul Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781450326711

One of the challenges in designing high-performance FPGA applications is fine-tuning the use of limited on-chip memory storage among many buffers in an application. To achieve desired performance the designer faces the burden of packaging such buffers into on-chip memories and manually optimizing the utilization of each memory and the throughput of each buffer. In addition, the application memories may not match the word width or depth of the physical on-chip memories available on the FPGA. This process is time consuming and non-trivial, particularly with a large number of buffers of various depths and bit widths. We propose a tool, MPack, which globally optimizes on-chip memory use across all buffers for stream applications. The goal is to speed up development time by providing rapid design space exploration and relieving the designer of lengthy low-level iterations. We introduce new high-level pragmas allowing the user to specify global memory requirements, such as an application's on-chip memory budget and data throughput. We allow the user to quickly generate a large number of memory solutions and explore the trade-off between memory usage and achievable throughput. To demonstrate the effectiveness of our tool, we apply the new high-level pragmas to an image processing benchmark. MPack effectively explores the design space and is able to produce a large number of memory solutions ranging from 10 to 100% in throughput, and from 12 to 100% in on-chip memory usage.

关键词： field programmable gate arrays (FPGA)

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CAD and routing architecture for interposer-based multi-FPGA systems 14

CAD and routing architecture for interposer-based multi-FPGA...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Pereira, Andre Hahn Betz, Vaughn Computer and Digital Systems Engineering Department-Escola Politécnica University of São Paulo São Paulo SP Brazil Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

Interposer-based multi-FPGA systems are composed of mul-tiple FPGA dice connected through a silicon interposer. Such devices allow larger FPGA systems to be built than one monolithic die can accomodate and are now commercially available. An open question, however, is how efficient such systems are compared to a monolithic FPGA, as the num-ber of signals passing between dice is reduced and the signal delay between dice is increased in an interposer system vs. a monolithic FPGA. We create a new version of VPR to investigate the archi-tecture of such systems, and show that by modifying the placement cost function to minimize the number of signals that must cross between dice we can reduce routing demand by 18% and delay by 2%. We also show that the signal count between dice and the signal delay between dice are key archi-tecture parameters for interposer-based FPGA systems. We find that if an interposer supplies (between dice) 60% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is little impact on the routability of circuits. Smaller routing capacities in the interposer do im-pact routability however: minimum channel width increases by 20% and 50% when an interposer supplies only 40% and 30% of the within-die routing, respectively. The interposer also impacts delay, increasing circuit delay by 34% on aver-age for a 1 ns interposer signal delay and a four-die system. Reducing the interposer delay has a greater benefit in im-proving circuit speed than does reducing the number of dice in the system.

关键词： field programmable gate arrays (FPGA)

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