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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Towards interconnect-adaptive packing for FPGAs 14

Towards interconnect-adaptive packing for FPGAs

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Luu, Jason Rose, Jonathan Anderson, Jason Dept. Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450326711

In order to investigate new FPGA logic blocks, FPGA ar-chitects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to cre-ate such CAD tools can be a time-consuming process that can significantly limit the number and variety of architec-tures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from im-practically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being in-vestigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common inter-connect structures that are used to create many kinds of use-ful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing , pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modi-fications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultane-ously expanding the scope of architectures that can be ex-plored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower crit-ical path delay. We obtain a 6 to 7-fold speedup for archi-tectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

关键词： field programmable gate arrays (FPGA)

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[email protected] all-programmable SoC ecosystem 14

[email protected] all-programmable SoC ecosystem

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Antonio Filgueras Eduard Gil Daniel Jimenez-Gonzalez Carlos Alvarez Xavier Martorell Jan Langer Juanjo Noguera Kees Vissers Barcelona Supercomputing Center - BSC-CNS Barcelona Spain Universitat Politecnica de Catalunya - UPC Barcelona Spain Xilinx Inc. Dublin Ireland Xilinx inc. San Jose CA USA

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： task dataflow models automatic hardware generation framework heterogenous parallel programming model

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Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a FPGA provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for FPGAs using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire FPGA based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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FPGA'11 - proceedings of the 2011 acm/sigda international symposium on field programmable gate arrays

FPGA'11 - Proceedings of the 2011 ACM/SIGDA International Sy...

引用

2011 19th acm/sigda international symposium on field programmable gate arrays, FPGA'11

ISBN: (纸本)9781450305549

The proceedings contain 37 papers. The topics discussed include: comparing FPGA vs. custom CMOs and the impact on processor microarchitecture;VEGAS: soft vector processor with scratchpad memory;leap scratchpads: automatic memory and cache management for reconfigurable logic;NETTM: faster and easier synchronization for soft multicores via transactional memory;LegUp: high-level synthesis for FPGA-based processor/accelerator systems;automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs;Torc: towards an open-source tool flow;FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting;a platform for high level synthesis of memory-intensive image processing algorithms;energy-efficient specialization of functional units in a coarse-grained reconfigurable array;and DEEP: an iterative FPGA-based many-core emulation system for chip verification and architecture research.

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Improving bitstream compression by modifying FPGA architecture 13

Improving bitstream compression by modifying FPGA architectu...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Location, location, location - The role of spatial locality in asymptotic energy minimization 13

Location, location, location - The role of spatial locality ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： DeHon, André M. Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Locality exploitation is essential to asymptotic energy minimization for gate array netlist evaluation. Naive implementations that ignore locality, including flat crossbars and simple processors based on monolithic memories, can require O(N2) energy for an N node graph. Specifically, it is important to exploit locality (1) to reduce the size of the description of the graph, (2) to reduce data movement, and (3) to reduce instruction movement. FPGAs exploit all three. FPGAs with a Rent Exponent p © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Faithful single-precision floating-point tangent for FPGAs 13

Faithful single-precision floating-point tangent for FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre High Wycombe United Kingdom

ISBN: (纸本)9781450318877

This paper presents an FPGA-specific implementation of the floating-point tangent function. The implementation inputs values in the interval [-π/2,π/2], targets the IEEE-754 single-precision format and has an accuracy of 1 ulp. The proposed work is based on a combination of mathematical identities and properties of the tangent function in floating point. The architecture was designed having the {Stratix-IV} DSP and memory blocks in mind but should map well on any contemporary FPGA featuring embedded multiplier and memory blocks. It outperforms generic polynomial approximation targeting the same resource spectrum and provides better resources trade-offs than classical CORDIC-based *** presented work is widely available as being part of the Altera DSP Builder Advanced Blockset. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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A remote memory access infrastructure for global address space programming models in FPGAs 13

A remote memory access infrastructure for global address spa...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Willenberg, Ruediger Chow, Paul Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for FPGA and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom FPGA cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-FPGA system with processors as well as custom hardware nodes. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Towards simulator-like observability for FPGAs: A virtual overlay network for trace-buffers 13

Towards simulator-like observability for FPGAs: A virtual ov...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Hung, Eddie Wilton, Steven J.E. Dept. of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450318877

The rising complexity of verification has led to an increase in the use of FPGA prototyping, which can run at significantly higher operating frequencies and achieve much higher coverage than logic simulations. However, a key challenge is observability into these devices, which can be solved by embedding trace-buffers to record on-chip signal values. Rather than connecting a predetermined subset of circuits signals to dedicated trace-buffer inputs at compile-time, in this work we propose that a virtual overlay network is built to multiplex all on-chip signals to all on-chip trace-buffers. Subsequently, at debug-time, the designer can choose a signal subset for observation. To minimize its overhead, we build this network out of unused routing multiplexers, and by using optimal bipartite graph matching techniques, we show that any subset of on-chip signals can be connected to 80-90% of the maximum trace-buffer capacity in less than 50 seconds. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Architectural enhancements in Stratix V™ 13

Architectural enhancements in Stratix V™

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Lewis, David Cashman, David Chan, Mark Chromczak, Jeffery Lai, Gary Lee, Andy Vanderhoek, Tim Yu, Haiming Altera Corporation 101 Innovation Drive San Jose CA 95134 United States Altera Corporation 150 Bloor St W. Toronto ON M5S 2X9 Canada

ISBN: (纸本)9781450318877

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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