检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

578 篇 会议
31 篇 期刊文献

馆藏范围

609 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

522 篇 工学
- 470 篇 计算机科学与技术...
- 289 篇 软件工程
- 228 篇 电子科学与技术（可...
- 157 篇 电气工程
- 86 篇 信息与通信工程
- 36 篇 控制科学与工程
- 35 篇 动力工程及工程热...
- 23 篇 机械工程
- 14 篇 生物工程
- 12 篇 仪器科学与技术
- 10 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 5 篇 材料科学与工程（可...
- 3 篇 农业工程
201 篇 理学
- 166 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 15 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
57 篇 管理学
- 48 篇 管理科学与工程(可...
- 30 篇 工商管理
- 10 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 教育学
- 3 篇 教育学
3 篇 农学
1 篇 医学

主题

261 篇 field programmab...
174 篇 field programmab...
39 篇 clocks
35 篇 signal processin...
34 篇 estimation
34 篇 filtration
33 篇 modulation
33 篇 ofdm
31 篇 fpga
8 篇 field-programmab...
7 篇 fpgas
7 篇 computer archite...
7 篇 systolic arrays
7 篇 optimization
7 篇 high-level synth...
7 篇 field-programmab...
7 篇 reconfigurable c...
6 篇 hardware
6 篇 field programmab...
5 篇 routing

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 xilinx
4 篇 univ british col...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 pasca bogdan
7 篇 constantinides g...
7 篇 chow paul
6 篇 wilton steven j....
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

602 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是281-290 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

来源：评论

学校读者我要写书评

暂无评论

Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on FPGA 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on FPGA for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Leveraging latency-insensitivity to ease multiple FPGA design 12

Leveraging latency-insensitivity to ease multiple FPGA desig...

引用

2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

作者： Fleming, Kermin Elliott Adler, Michael Pellauer, Michael Parashar, Angshuman Mithal, Arvind Emer, Joel Intel Corporation VSSAD Group Hudson MA United States Massachusetts Institute of Technology Computer Science and A.I. Laboratory Cambridge MA United States

ISBN: (纸本)9781450311557

Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. © 2012 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Impact of FPGA architecture on resource sharing in high-level synthesis 12

Impact of FPGA architecture on resource sharing in high-leve...

引用

2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

作者： Hadjis, Stefan Canis, Andrew Anderson, Jason H. Choi, Jongsok Nam, Kevin Brown, Stephen Czajkowski, Tomasz ECE Department University of Toronto Toronto ON Canada Altera Toronto Technology Centre Toronto ON Canada

ISBN: (纸本)9781450311557

Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs). © 2012 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FPGA'10 - proceedings of the 18th acm sigda international symposium on field-programmable gate arrays

FPGA'10 - Proceedings of the 18th ACM SIGDA International Sy...

引用

18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

ISBN: (纸本)9781605589114

The proceedings contain 34 papers. The topics discussed include: FPGA prototyping of an AMBA-based Windows-compatible SoC;predicting the performance of application-specific NoCs implemented on FPGAs;energy efficient sensor node implementations;high throughput and large capacity pipelined dynamic search tree on FPGA;FPMR: MapReduce framework on FPGA: a case study of RankBoost acceleration;Axel: a heterogeneous cluster with FPGAs and GPUs;building a faster Boolean matcher using bloom filter;scalable network virtualization using FPGAs;maximizing area-constrained partial fault tolerance in reconfigurable logic;FPGA based chip emulation system for test development and verification of analog and mixed signal circuits;a semi-automatic Toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning;and a dependency graph based methodology for parallelizing HLL applications on FPGA.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A Complete Power Estimation Methodology for DSP Blocks in FPGAs

A Complete Power Estimation Methodology for DSP Blocks in FP...

引用

13th international symposium on Quality Electronic Design (ISQED)

作者： Hassan, Hassan Abdallah, Nizar Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781467310369;9781467310352

This work proposes a complete commercial power model for DSP blocks in FPGAs. A pin activities model is developed to estimate the transitions densities at the output of the DSP blocks given the switching activities at the inputs. Such a pin activities model is important in estimating power dissipation during the pre-layout design phase. The power model estimates the total power dissipation in the DSP blocks using the knowledge of all the transitions densities of the inputs and outputs, which are estimated by the proposed pin activities model. The average error of the proposed power model on the design level is less than 2%.

关键词： powered models Digital signal processing Desmoplakin Gene power estimation Power dissipation PIN Bone Nails field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

引用

acm/sigda international symposium on field programmable gate arrays - FPGA 2010年 iii页

作者： Cheung, Peter Wawrzynek, John Imperial College London United Kingdom University of California Berkeley CA United States

来源：评论

学校读者我要写书评

暂无评论

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in FPGAs with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

来源：评论

学校读者我要写书评

暂无评论

A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on FPGAs [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an FPGA implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 FPGA using the four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger FPGAs being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these FPGAs.

关键词： architecture fpga simd image processor array

来源：评论

学校读者我要写书评

暂无评论

Thermal and Power Characterization of field-programmable gate arrays 11

Thermal and Power Characterization of Field-Programmable Gat...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Nowroz, Abdullah Nazma Reda, Sherief Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9781450305549

In this paper we propose new techniques for thermal and power characterization of field programmable gate arrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.

关键词： Thermal characterization sensors power mapping

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共61页 << < 25 26 27 28 29 30 31 32 33 34 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：