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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network 24

GraFlex: Flexible Graph Processing on FPGAs through Customiz...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Su, Chunyou Du, Linfeng Liang, Tingyuan Lin, Zhe Wang, Maolin Sinha, Sharad Zhang, Wei The Hong Kong University of Science and Technology Kowloon Hong Kong Sun Yat-sen University Guangdong ShenZhen China New Territories Hong Kong Indian Institute of Technology Goa Goa India

ISBN: (纸本)9798400704185

Graph processing system design has been widely considered to be a challenging topic due to the mismatch between the computational throughput requirement and the memory bandwidth. Recent works try to deliver better graph processing systems by taking advantage of application-specific architectures and emerging high-bandwidth memory on FPGAs. However, there is still ample room for improvements regarding flexibility, scalability, and usability. This paper presents GraFlex, a flexible scatter-gather graph processing framework on FPGAs with scalable interconnection networks. It adopts the Bulk-Synchronous Parallel (BSP) paradigm for global control and synchronization, enabling rapid deployment of performant graph processing systems through HLS-based design flows. GraFlex conducts software-hardware co-optimization to boost system performance. It configures the compact graph format, partition scheme, and memory channel allocation strategy to support scalable designs. Resource-efficient multi-stage butterfly interconnection network achieves on-device data communication and facilitates throughput matching. To handle fragmented memory requests, we propose coalesced memory access engines to improve bandwidth utilization. GraFlex is comprehensively evaluated with various graph applications and real-world datasets. Our results show up to 2.09\texttimes average speedup in traversal throughput over the existing state-of-the-art work with a non-negligible reduction in power and resource consumption. A case study of the breadth-first search (BFS) application shows a 6.58\texttimes speedup in average algorithm throughout with proper implementation choices enabled by the scatter-gather mechanism implemented. The BFS study also reports an almost linear throughput scaling versus the number of processing elements (PEs) and memory channels. © 2024 acm.

关键词： field programmable gate arrays (FPGA)

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HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs 24

HiSpMV: Hybrid Row Distribution and Vector Buffering for Imb...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Rajashekar, Manoj B. Tian, Xingyu Fang, Zhenman Simon Fraser University BurnabyBC Canada

ISBN: (纸本)9798400704185

Sparse matrix-vector multiplication (SpMV) is a fundamental operation in numerous applications such as scientific computing, machine learning, and graph analytics. While recent studies have made great progress in accelerating SpMV on HBM-equipped FPGAs, there are still multiple remaining challenges to efficiently accelerate imbalanced SpMV where the distribution of non-zeros in the sparse matrix is imbalanced across different rows. First, the imbalanced workload distribution among the parallel processing elements (PEs) leads to PE under-utilization and performance degradation. Second, the read-after-write dependency of the long-latency floating-point accumulation on the output vector causes pipeline stalls inside the PE, and existing scheduling solutions for balanced matrices no longer work effectively for imbalanced ones. Third, the memory access latency for the often overlooked input vector becomes a new performance bottleneck after the SpMV acceleration. To address the above challenges, in this work, we propose HiSpMV to accelerate imbalanced SpMV on HBM-equipped FPGAs. First, we design a hybrid row distribution network to enable both inter-row and intra-row distribution to achieve more balance. Second, we implement fully pipelined floating-point accumulation on the output vector using a combination of an adder tree and circular buffer. Third, we design a hybrid buffering technique to optimize the input vector loading from off-chip memory by dynamically switching between private partitioned buffers and shared ping-pong buffers. Lastly, we also developed an automation framework to automatically generate the optimized HiSpMV accelerator based on the user configurations. Experimental results demonstrate that HiSpMV achieves a geomean speedup of 13.7x (up to 60x) for highly imbalanced matrices, compared to state-of-the-art SpMV accelerator Serpens on the AMD-Xilinx Alveo U280 HBM-based FPGA. Compared to Intel MKL running on a 24-core Xeon Silver 4214 CPU, HiSpMV achi

关键词： field programmable gate arrays (FPGA)

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LevelST: Stream-based Accelerator for Sparse Triangular Solver 24

LevelST: Stream-based Accelerator for Sparse Triangular Solv...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： He, Zifan Song, Linghao Lucas, Robert F. Cong, Jason University of California Los Angeles Los Angeles United States Ansys Inc. Livermore United States

ISBN: (纸本)9798400704185

Over the past decade, much progress has been made to advance the acceleration of sparse linear operators such as SpMM and SpMV on FPGAs. Nevertheless, few works have attempted to address sparse triangular solver (SpTRSV) acceleration, and the performance boost is limited. SpTRSV is an elementary linear operator for many numerical methods, such as the least-square method. These methods, among others, are widely used in various areas, such as physical simulation and signal processing. Therefore, accelerating SpTRSV is crucial. However, many challenges impede accelerating SpTRSV, including (1) resolving dependencies between elements during forward or backward substitutions, (2) random access and unbalanced workloads across memory channels due to sparsity, (3) latency incurred by off-chip memory access for large matrices or vectors, and (4) data reuse for an unpredictable data sharing pattern. To address these issues, we have designed LevelST, the first FPGA accelerator leveraging high bandwidth memory (HBM) for solving sparse triangular systems. LevelST features (1) algorithm-hardware co-design of stream-based dependency resolution with reduced off-chip data movement, (2) resource sharing that improves resource utilization to scale up the architecture, (3) index modulo scheduling to balance workload, and (4) selective data prefetching from off-chip memory. LevelST is prototyped on an AMD Xilinx U280 HBM FPGA and evaluated with 16 sparse triangular matrices. Compared with the NVIDIA V100 and RTX 3060 GPUs over the cuSPARSE library, LevelST achieves a 2.65x speedup and 9.82x higher energy efficiency than the best of the V100 GPU and RTX 3060 GPU. The code is released on https://***/OswaldHe/LevelST (DOI: https://***/10.5281/zenodo.10463345). © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs 24

FlightLLM: Efficient Large Language Model Inference with a C...

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32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Zeng, Shulin Liu, Jun Dai, Guohao Yang, Xinhao Fu, Tianyu Wang, Hongyi Ma, Wenheng Sun, Hanbo Li, Shiyao Huang, Zixiao Dai, Yadong Li, Jintao Wang, Zehao Zhang, Ruoyu Wen, Kairui Ning, Xuefei Wang, Yu Tsinghua University Infinigence-AI China Shanghai Jiao Tong University Infinigence-AI China Tsinghua University China Infinigence-AI

ISBN: (纸本)9798400704185

Transformer-based Large Language Models (LLMs) have made a significant impact on various domains. However, LLMs' efficiency suffers from both heavy computation and memory overheads. Compression techniques like sparsification and quantization are commonly used to mitigate the gap between LLM's computation/memory overheads and hardware capacity. However, existing GPU and transformer-based accelerators cannot efficiently process compressed LLMs, due to the following unresolved challenges: low computational efficiency, underutilized memory bandwidth, and large compilation overheads. This paper proposes FlightLLM, enabling efficient LLMs inference with a complete mapping flow on FPGAs. In FlightLLM, we highlight an innovative solution that the computation and memory overhead of LLMs can be solved by utilizing FPGA-specific resources (e.g., DSP48 and heterogeneous memory hierarchy). We propose a configurable sparse DSP chain to support different sparsity patterns with high computation efficiency. Second, we propose an always-on-chip decode scheme to boost memory bandwidth with mixed-precision support. Finally, to make FlightLLM available for real-world LLMs, we propose a length adaptive compilation method to reduce the compilation overhead. Implemented on the Xilinx Alveo U280 FPGA, FlightLLM achieves 6.0× higher energy efficiency and 1.8× better cost efficiency against commercial GPUs (e.g., NVIDIA V100S) on modern LLMs (e.g., LLaMA2-7B) using vLLM and SmoothQuant under the batch size of one. FlightLLM beats NVIDIA A100 GPU with 1.2× higher throughput using the latest Versal VHK158 FPGA. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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FPIA: field-programmable Ising arrays with In-Memory Computing 24

FPIA: Field-Programmable Ising Arrays with In-Memory Computi...

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29th acm/IEEE international symposium on Low Power Electronics and Design, ISLPED 2024

作者： Hutchinson, George Higgins Sifferman, Ethan Bhattacharya, Tinish Kwon, Dongseok Strukov, Dmitri B Department of Electrical and Computer Engineering University of California at Santa Barbara Santa BarbaraCA United States

ISBN: (纸本)9798400706882

Ising Machines, a promising approach for solving combinatorial optimization problems, are naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A naïve in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. This approach, however, uses resources inefficiently due to the inherent sparsity of practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. This technique, however, requires interconnecting sub-arrays, which incurs overhead. In response, we present FPIA, an in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays. We adapt open-source tools to optimize problem embedding and model overhead. Modeling results of benchmark problems for the developed architecture show up to 10x increase in density and speed compared to the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to acm.

关键词： Ising model

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Multi-input Serial Adders for FPGA-like Computational Fabric 22

Multi-input Serial Adders for FPGA-like Computational Fabric

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Schmit, Herman Denton, Matthew Google Research Mountain ViewCA United States

ISBN: (纸本)9781450391498

In this paper, we present a new functional unit to replace the LUT in an FPGA-like computational fabric designed specifically for use to accelerate instance-specific sparse integer matrix multiplication. We use a suite of matrices, the VPR place-and-route tool, and modern architecture representations of the interconnect to examine this architectural idea. The new cell, called the K - ADD, increases density by 2.5× to 4×, and increases performance by 8% to 30% by simultaneously increasing the clock rate and reducing the number of cycles to compute the product. This benefit magnifies the two-orders-of-magnitude advantage of using instance-specific matrix multipliers demonstrated in prior work. We investigate the cluster size, N, across multiple technology nodes. In that investigation, we see a sustained benefit to a larger cluster size (N=8). This observation holds for both netlists mapped to a 6 - LUT and to a 6 - ADD, which implies this behavior has more to do with the peculiar structure of these matrix multiplication netlists, not the different functional unit. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs 22

Towards Agile DNN Accelerator Design Using Incremental Synth...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Xiao, Qingcheng Liang, Yun Peking University Beijing China

ISBN: (纸本)9781450391498

Hardware-software co-design is the new trend for deep neural network and FPGA accelerator development, which iteratively revises and tunes the full system. The bottleneck of the approach lies in the time-consuming hardware synthesis. In this paper, we propose an incremental synthesis framework Acoda to rapidly design DNN accelerators on FPGAs. Based on the observation that most revisions to DNNs are minor and local, Acoda reuses existing hardware modules and incrementally modifies the accelerator. It first detects the software revisions using a graph edit distance algorithm. Then, it maps the software revisions to hardware revisions through a multi-level reuse hierarchy. As a result, Acoda speeds up the design process by 9.31X to 34.17X and achieves performance results comparable to off-the-shelf accelerators. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

The emergence of Internet of Things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since field-programmable gate arrays (FPGAs) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in FPGAs is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on FPGAs. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-Things (IoT) field-programmable gate Array (FPGA) Hardware Security Design Methodology

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FPGA 2017 - proceedings of the 2017 acm/sigda international symposium on field-programmable gate arrays

FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International ...

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2017 acm/sigda international symposium on field-programmable gate arrays, FPGA 2017

ISBN: (纸本)9781450343541

The proceedings contain 32 papers. The topics discussed include: the role of FPGAs in deep learning;accelerating binarized convolutional neural networks with software-programmable FPGAs;improving the performance of OpenCL-based FPGA accelerator for convolutional neural network;frequency domain acceleration of convolutional neural networks on CPU-FPGA shared memory system;FINN: a framework for fast, scalable binarized neural network inference;quality-time tradeoffs in component-specific mapping: how to train your dynamically reconfigurable array of gates with outrageous network-delays;synchronization constraints for interconnect synthesis;automatic construction of program-optimized FPGA memory networks;a parallelized iterative improvement approach to area optimization for LUT-based technology mapping;a new approach to automatic memory banking using trace-based address mining;dynamic hazard resolution for pipelining irregular loops in high-level synthesis;and secure function evaluation using an FPGA overlay architecture.

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How to shrink my FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics 22

How to shrink my FPGAs - Optimizing Tile Interfaces and the ...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Chung, King Lok Dao, Nguyen Yu, Jing Koch, Dirk Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450391498

Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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