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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration 11

Eliminating the Memory Bottleneck: An FPGA-based Solution fo...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China

ISBN: (纸本)9781450305549

Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale with the future increase of FPGA capacities.

关键词： field programmable gate arrays (FPGA) Reverse Time Migration (RTM)

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Scalable and deterministic timing-driven parallel placement for FPGAs 11

Scalable and deterministic timing-driven parallel placement ...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Wang, Chris C. Lemieux, Guy G.F. Dept. of ECE University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

This paper describes a parallel implementation of the timing-driven VPR∼5.0 simulated annealing engine. By restricting the move distance to a confined neighborhood, it is possible to consider a large number of non-conflicting moves in parallel and achieve a deterministic result. The full timing-driven algorithm is parallelized, including the detailed timing analysis updates done periodically while placement progresses. The limited move slightly degrades the placement quality, but this is necessary to expose greater degrees of parallelism. The overall bounding box metric degrades about 11% and critical path delay metric degrades about 8% compared to VPR's original algorithm, but we show the amount of degradation is independent of the number of threads. Overall, the parallel implementation scales to a speedup of 123× using 25 threads compared to VPR. With additional tuning effort, we believe the algorithm can be scaled to a larger number of threads, perhaps even run on a GPU, with little additional quality degradation. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

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Towards Scalable FPGA CAD Through Architecture 11

Towards Scalable FPGA CAD Through Architecture

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19th Annual acm international symposium on field-programmable gate arrays

作者： Chin, Scott Y. L. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical. Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

关键词： field-programmable gate arrays FPGAs Architecture CAD Run-time

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Real-time high-definition stereo matching on FPGA 11

Real-time high-definition stereo matching on FPGA

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Zhang, Lu Zhang, Ke Chang, Tian Sheuan Lafruit, Gauthier Kuzmanov, Georgi Krasimirov Verkest, Diederik Delft University of Technology Mekelweq 4 2600GA Delft Netherlands IMEC Kapeldreef 75 B-3001 Leuven Belgium National Chiao Tung University 1001 TaHsueh Rd. Hsinchu Taiwan

ISBN: (纸本)9781450305549

Although many fast stereo matching designs have been proposed in the past decades, it is still very challenging to achieve real-time speed at high definition resolution while maintaining high matching accuracy. In this paper, we propose a real-time high definition stereo matching design on FPGA. By using the Mini-Census transform and the Cross-based cost aggregation, the proposed algorithm is robust to radiometric differences and produces accurate disparity maps. The algorithm modules have been optimized for efficient hardware implementations and instantiated in an SoC environment. Implemented on a single EP3SL150 FPGA, our design achieves 60 frames per second for 1024 × 768 stereo images. Evaluated with the Middlebury stereo benchmark, the proposed design also delivers leading stereo matching accuracy among prior related work. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

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A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Power 11

A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Po...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Greene, Jonathan Kaptanoglu, Sinan Feng, Wenyi Hecht, Volker Landry, Joel Li, Fei Krouglyanskiy, Anton Morosan, Mihai Pevzner, Val Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781450305549

This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the IT flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

关键词： FPGA architecture flash memory Clos network built-in self-test programmable routing input interconnection block IIB packing

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Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect 11

Architecture description and packing for logic blocks with h...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Luu, Jason Anderson, Jason Helge Rose, Jonathan Scott Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450305549

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

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proceedings of the 7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

Proceedings of the 7th ACM SIGDA International Symposium on ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

ISBN: (纸本)9781605584102

The proceedings contain 34 papers. The topics discussed include: emerging application domains - research challenges and opportunities for FPGAs;towards automated ECOs in FPGAs;clock power reduction for Virtex-5 FPGAs;choose-your-own-adventure routing: lightweight load-time defect avoidance;towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs;a comparison of via-programmable gate array logic cell circuits;a comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation;a high-performance FPGA architecture for restricted Boltzmann machines;FPGA-based front-end electronics for positron emission tomography;FPGA-based face detection system using Haar classifiers;a 17ps time-to-digital converter implemented in 65nm FPGA technology;and FPGA technology mapping with encoded libraries and staged priority cuts.

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mrFPGA: A novel FPGA architecture with memristor-based reconfiguration 11

mrFPGA: A novel FPGA architecture with memristor-based recon...

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proceedings of the 2011 IEEE/acm international symposium on Nanoscale Architectures

作者： Cong, Jason Xiao, Bingjun Department of Computer Science University of California Los Angeles CA United States

ISBN: (纸本)9781457709944

In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only) 11

Memory based computing: reshaping the fine-grained logic in ...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Somnath Paul Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450305549

Conventional field programmable gate Array (FPGA) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. The proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based FPGA. Simulation results show that compared to a clustered FPGA model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III FPGA platform from Altera.

关键词： memory based computation field programmable gate array (fpga) recongurable hardware

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