检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

578 篇 会议
31 篇 期刊文献

馆藏范围

609 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

522 篇 工学
- 470 篇 计算机科学与技术...
- 289 篇 软件工程
- 228 篇 电子科学与技术（可...
- 157 篇 电气工程
- 86 篇 信息与通信工程
- 36 篇 控制科学与工程
- 35 篇 动力工程及工程热...
- 23 篇 机械工程
- 14 篇 生物工程
- 12 篇 仪器科学与技术
- 10 篇 建筑学
- 9 篇 土木工程
- 8 篇 冶金工程
- 8 篇 化学工程与技术
- 7 篇 生物医学工程（可授...
- 5 篇 光学工程
- 5 篇 材料科学与工程（可...
- 3 篇 农业工程
201 篇 理学
- 166 篇 数学
- 36 篇 物理学
- 20 篇 统计学（可授理学、...
- 15 篇 生物学
- 7 篇 系统科学
- 6 篇 化学
57 篇 管理学
- 48 篇 管理科学与工程(可...
- 30 篇 工商管理
- 10 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 8 篇 社会学
3 篇 教育学
- 3 篇 教育学
3 篇 农学
1 篇 医学

主题

261 篇 field programmab...
174 篇 field programmab...
39 篇 clocks
35 篇 signal processin...
34 篇 estimation
34 篇 filtration
33 篇 modulation
33 篇 ofdm
31 篇 fpga
8 篇 field-programmab...
7 篇 fpgas
7 篇 computer archite...
7 篇 systolic arrays
7 篇 optimization
7 篇 high-level synth...
7 篇 field-programmab...
7 篇 reconfigurable c...
6 篇 hardware
6 篇 field programmab...
5 篇 routing

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 xilinx
4 篇 univ british col...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 northwestern uni...
3 篇 fudan university

作者

20 篇 rose jonathan
20 篇 cong jason
11 篇 betz vaughn
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 hauck scott
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 pasca bogdan
7 篇 constantinides g...
7 篇 chow paul
6 篇 wilton steven j....
6 篇 li fei
5 篇 anderson jason h...
5 篇 dehon andre
5 篇 cheung peter y. ...
5 篇 ienne paolo

语言

602 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是371-380 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Performance benefits of monolithically stacked 3D-FPGA 06

Performance benefits of monolithically stacked 3D-FPGA

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Lin, Mingjie Gamal, Abbas El Lu, Yi-Chang Wong, Simon Department of Electrical Engineering Stanford University CA 94305 United States

ISBN: (纸本)1595932925

The performance benefits of a monolithically stacked 3D-FPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-FPGA fabric is used as a baseline for quantifying the relative improvements in logic density, delay, and power consumption achieved by such a 3D-FPGA. It is assumed that only the pass-transistor switches and configuration memory cells can be moved to the top layers and that the 3D-FPGA employs the same logic block and programmable interconnect architecture as the baseline 2D-FPGA. Assuming a configuration memory cell that is ≤ 0.7 the area of an SRAM cell and pass-transistor switches having the same characteristics as nMOS devices in the CMOS layer are used, it is shown that a monolithically stacked 3D-FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2D-FPGA fabricated in the same 65nm technology node. Copyright 2006 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Power-aware RAM mapping for FPGA embedded memory blocks 06

Power-aware RAM mapping for FPGA embedded memory blocks

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Tessier, Russell Betz, Vaughn Neto, David Gopalsamy, Thiagaraja Department of Electrical and Computer Engineering University of Massachusetts Amherst MA United States Altera Toronto Technology Centre 151 Bloor St Toronto Ont. Canada Altera Corporation 101 Innovation Drive San Jose CA United States

ISBN: (纸本)1595932925

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance. Copyright 2006 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Design of a Single Event Upset (SEU) mitigation technique for programmable devices 06

Design of a Single Event Upset (SEU) mitigation technique fo...

引用

7th international symposium on Quality Electronic Design

作者： Baloch, S. Arslan, T. Stoica, A. Alba Centre Inst Syst Level Integrat Alba Campus Livingston EH54 7EG Scotland Univ Edinburgh Sch Elect & Engg Edinburgh EH8 9YL Midlothian Scotland NASA Jet Propuls Lab Pasadena CA 91109 USA

ISBN: (纸本)0769525237

This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.

关键词： Single event upset field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation programmable logic arrays Latches

来源：评论

学校读者我要写书评

暂无评论

Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

引用

7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

来源：评论

学校读者我要写书评

暂无评论

Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs 06

Analysis and experimental results of an FPGA-based strategy ...

引用

7th international symposium on Quality Electronic Design

作者： De Venuto, Daniela Reyneri, Leonardo Politecn Bari Bari Italy Politecn Torino Turin Italy

ISBN: (纸本)0769525237

This work describes an intensive investigation on the test strategy known as polynomial fitting that uses FPGA generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. The proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.

关键词： Production Circuit testing Automatic testing Polynomials Built-in self-test Signal generators Linearity Histograms Performance evaluation field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Probabilistic delay budgeting for soft realtime applications 06

Probabilistic delay budgeting for soft realtime applications

引用

7th international symposium on Quality Electronic Design

作者： Ghiasi, Soheil Huan, Po-Kuan Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769525237

Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. This paradigm shaft calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multimedia applications on FPGAs show about 20% and 19% average energy and area improvement, respectively.

关键词： Timing Delay effects Hardware Flow graphs Application software Algorithm design and analysis Data flow computing Design methodology Stochastic processes field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Dual-Vt design of FPGAs for subthreshold leakage tolerance 06

Dual-Vt design of FPGAs for subthreshold leakage tolerance

引用

7th international symposium on Quality Electronic Design

作者： Kumar, Akhilesh Anis, Mohab Univ Waterloo Dept ECE 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769525237

In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures.

关键词： field programmable gate arrays Subthreshold current Routing Switches Design automation Circuits Threshold voltage Logic design Sleep MOS devices

来源：评论

学校读者我要写书评

暂无评论

A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

引用

proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. This architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. Through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). These switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

关键词：

来源：评论

学校读者我要写书评

暂无评论

2004 acm/sigda twelfth international symposium on field programmable gate arrays

2004 ACM/SIGDA twelfth international symposium on field prog...

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Tessier, Russ Schmit, Herman

No abstract available

关键词：

来源：评论

学校读者我要写书评

暂无评论

acm/sigda twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

ACM/SIGDA twelfth ACM international symposium on field-progr...

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

The proceedings contains 24 papers from the acm/sigda international symposium on field programmable gate arrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluation of low leakage design techniques for field programmable gate arrays;reducing leakage energy in FPGAs using region constrained placement;an embedded true random number generator for FPGAs;a synthesis oriented omniscient manual editor;nanowire-based sublithographic programmable logic arrays;and highly pipelined asynchronous FPGAs.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共61页 << < 34 35 36 37 38 39 40 41 42 43 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：